frontend/ecc: move generic part of ECC to LiteX
This commit is contained in:
Florent Kermarrec
parent
8646b2e2c4
commit
2ecb0534ec
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@ -16,157 +16,15 @@ Limitations:
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- Byte enable not supported for writes.
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"""
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from functools import reduce
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from operator import xor
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from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.stream import *
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from litex.soc.cores.ecc import *
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from litedram.common import wdata_description, rdata_description
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def compute_m_n(k):
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m = 1
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while (2**m < (m + k + 1)):
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m = m + 1;
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n = m + k
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return m, n
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def compute_syndrome_positions(m):
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r = []
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i = 1
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while i <= m:
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r.append(i)
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i = i << 1
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return r
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def compute_data_positions(m):
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r = []
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e = compute_syndrome_positions(m)
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for i in range(1, m + 1):
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if not i in e:
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r.append(i)
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return r
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def compute_cover_positions(m, p):
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r = []
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i = p
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while i <= m:
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for j in range(min(p, m - i + 1)):
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r.append(i + j)
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i += 2*p
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return r
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class SECDED:
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def place_data(self, data, codeword):
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d_pos = compute_data_positions(len(codeword))
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for i, d in enumerate(d_pos):
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self.comb += codeword[d-1].eq(data[i])
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def extract_data(self, codeword, data):
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d_pos = compute_data_positions(len(codeword))
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for i, d in enumerate(d_pos):
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self.comb += data[i].eq(codeword[d-1])
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def compute_syndrome(self, codeword, syndrome):
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p_pos = compute_syndrome_positions(len(codeword))
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for i, p in enumerate(p_pos):
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pn = Signal()
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c_pos = compute_cover_positions(len(codeword), 2**i)
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for c in c_pos:
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new_pn = Signal()
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self.comb += new_pn.eq(pn ^ codeword[c-1])
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pn = new_pn
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self.comb += syndrome[i].eq(pn)
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def place_syndrome(self, syndrome, codeword):
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p_pos = compute_syndrome_positions(len(codeword))
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for i, p in enumerate(p_pos):
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self.comb += codeword[p-1].eq(syndrome[i])
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def compute_parity(self, codeword, parity):
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self.comb += parity.eq(reduce(xor,
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[codeword[i] for i in range(len(codeword))]))
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class ECCEncoder(SECDED, Module):
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def __init__(self, k):
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m, n = compute_m_n(k)
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self.i = i = Signal(k)
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self.o = o = Signal(n + 1)
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# # #
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syndrome = Signal(m)
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parity = Signal()
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codeword_d = Signal(n)
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codeword_d_p = Signal(n)
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codeword = Signal(n + 1)
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# place data bits in codeword
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self.place_data(i, codeword_d)
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# compute and place syndrome bits
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self.compute_syndrome(codeword_d, syndrome)
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self.comb += codeword_d_p.eq(codeword_d)
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self.place_syndrome(syndrome, codeword_d_p)
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# compute parity
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self.compute_parity(codeword_d_p, parity)
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# output codeword + parity
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self.comb += o.eq(Cat(parity, codeword_d_p))
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class ECCDecoder(SECDED, Module):
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def __init__(self, k):
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m, n = compute_m_n(k)
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self.enable = Signal()
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self.i = i = Signal(n + 1)
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self.o = o = Signal(k)
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self.sec = sec = Signal()
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self.ded = ded = Signal()
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# # #
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syndrome = Signal(m)
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parity = Signal()
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codeword = Signal(n)
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codeword_c = Signal(n)
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# input codeword + parity
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self.compute_parity(i, parity)
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self.comb += codeword.eq(i[1:])
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# compute_syndrome
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self.compute_syndrome(codeword, syndrome)
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self.comb += If(~self.enable, syndrome.eq(0))
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# locate/correct codeword error bit if any and flip it
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cases = {}
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cases["default"] = codeword_c.eq(codeword)
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for i in range(1, 2**len(syndrome)):
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cases[i] = codeword_c.eq(codeword ^ (1<<(i-1)))
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self.comb += Case(syndrome, cases)
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# extract data / status
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self.extract_data(codeword_c, o)
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self.comb += [
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If(syndrome != 0,
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# double error detected
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If(~parity,
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ded.eq(1)
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# single error corrected
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).Else(
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sec.eq(1)
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)
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)
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]
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class LiteDRAMNativePortECCW(Module):
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def __init__(self, data_width_from, data_width_to):
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self.sink = sink = Endpoint(wdata_description(data_width_from))
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@ -13,92 +13,6 @@ from litex.gen.sim import *
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class TestECC(unittest.TestCase):
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def test_m_n(self):
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m, n = compute_m_n(15)
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self.assertEqual(m, 5)
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self.assertEqual(n, 20)
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def test_syndrome_positions(self):
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p_pos = compute_syndrome_positions(20)
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p_pos_ref = [1, 2, 4, 8, 16]
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self.assertEqual(p_pos, p_pos_ref)
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def test_data_positions(self):
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d_pos = compute_data_positions(20)
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d_pos_ref = [3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20]
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self.assertEqual(d_pos, d_pos_ref)
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def test_cover_positions(self):
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c_pos_ref = {
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0 : [1, 3, 5, 7, 9, 11, 13, 15, 17, 19],
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1 : [2, 3, 6, 7, 10, 11, 14, 15, 18, 19],
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2 : [4, 5, 6, 7, 12, 13, 14, 15, 20],
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3 : [8, 9, 10, 11, 12, 13, 14, 15],
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4 : [16, 17, 18, 19, 20]
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}
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for i in range(5):
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c_pos = compute_cover_positions(20, 2**i)
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self.assertEqual(c_pos, c_pos_ref[i])
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def test_ecc(self, k=15):
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class DUT(Module):
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def __init__(self, k):
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m, n = compute_m_n(k)
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self.flip = Signal(n + 1)
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# # #
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self.submodules.encoder = ECCEncoder(k)
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self.submodules.decoder = ECCDecoder(k)
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self.comb += self.decoder.i.eq(self.encoder.o ^ self.flip)
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def generator(dut, k, nvalues, nerrors):
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dut.errors = 0
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prng = random.Random(42)
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yield dut.decoder.enable.eq(1)
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for i in range(nvalues):
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data = prng.randrange(2**k-1)
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yield dut.encoder.i.eq(data)
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# FIXME: error when fliping parity bit
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if nerrors == 1:
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flip_bit1 = (prng.randrange(len(dut.flip)-2) + 1)
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yield dut.flip.eq(1<<flip_bit1)
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elif nerrors == 2:
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flip_bit1 = (prng.randrange(len(dut.flip)-2) + 1)
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flip_bit2 = flip_bit1
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while flip_bit2 == flip_bit1:
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flip_bit2 = (prng.randrange(len(dut.flip)-2) + 1)
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yield dut.flip.eq((1<<flip_bit1) | (1<<flip_bit2))
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yield
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# if less than 2 errors, check data
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if nerrors < 2:
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if (yield dut.decoder.o) != data:
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dut.errors += 1
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# if 0 error, verify sec == 0 / ded == 0
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if nerrors == 0:
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if (yield dut.decoder.sec) != 0:
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dut.errors += 1
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if (yield dut.decoder.ded) != 0:
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dut.errors += 1
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# if 1 error, verify sec == 1 / dec == 0
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elif nerrors == 1:
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if (yield dut.decoder.sec) != 1:
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dut.errors += 1
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if (yield dut.decoder.ded) != 0:
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dut.errors += 1
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# if 2 errors, verify sec == 0 / ded == 1
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elif nerrors == 2:
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if (yield dut.decoder.sec) != 0:
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dut.errors += 1
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if (yield dut.decoder.ded) != 1:
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dut.errors += 1
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for i in range(3):
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dut = DUT(k)
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run_simulation(dut, generator(dut, k, 128, i))
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self.assertEqual(dut.errors, 0)
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def test_ecc_wrapper(self):
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# 32 bits + 8 bits ecc
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port_from = LiteDRAMNativePort("both", 24, 32*8)
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