frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests)
This commit is contained in:
Florent Kermarrec
parent
19a0bd59d2
commit
30bacfeb1b
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@ -45,10 +45,12 @@ def cmd_layout(aw):
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("ready", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("adr", aw, DIR_M_TO_S),
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("lock", 1, DIR_S_TO_M),
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("lock", 1, DIR_S_TO_M), # only used internally
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("wdata_valid", 1, DIR_M_TO_S),
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("wdata_ready", 1, DIR_S_TO_M),
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("rdata_valid", 1, DIR_S_TO_M)
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("rdata_valid", 1, DIR_S_TO_M),
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("rdata_ready", 1, DIR_M_TO_S)
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]
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@ -73,9 +75,10 @@ class LiteDRAMInterface(Record):
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class LiteDRAMPort(Record):
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def __init__(self, aw, dw):
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def __init__(self, aw, dw, cd):
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self.aw = aw
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self.dw = dw
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self.cd = cd
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layout = cmd_layout(aw) + data_layout(dw)
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Record.__init__(self, layout)
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@ -46,7 +46,9 @@ class BankMachine(Module):
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settings.cmd_buffer_depth)
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self.submodules += cmd_buffer
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self.comb += [
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req.connect(cmd_buffer.sink, omit=["wdata_ready", "rdata_valid", "lock"]),
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req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready",
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"rdata_valid", "rdata_ready",
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"lock"]),
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cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
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req.lock.eq(cmd_buffer.source.valid),
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]
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@ -25,12 +25,14 @@ class LiteDRAMWishboneBridge(Module):
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)
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)
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fsm.act("WRITE_DATA",
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port.wdata_valid.eq(1),
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If(port.wdata_ready,
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wishbone.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ_DATA",
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port.rdata_ready.eq(1),
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If(port.rdata_valid,
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wishbone.ack.eq(1),
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NextState("IDLE")
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@ -4,8 +4,62 @@ from operator import or_
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from litex.gen import *
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from litex.gen.genlib import roundrobin
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from litex.soc.interconnect import stream
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from litedram.common import *
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class LiteDRAMAsyncAdapter(Module):
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def __init__(self, port_from, port_to):
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aw = port_from.aw
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dw = port_from.dw
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cd_from = port_from.cd
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cd_to = port_from.cd
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# # #
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cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 4)
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cmd_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cmd_fifo)
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self.submodules += cmd_fifo
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self.comb += [
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cmd_fifo.sink.valid.eq(port_from.valid),
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cmd_fifo.sink.we.eq(port_from.we),
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cmd_fifo.sink.adr.eq(port_from.adr),
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port_from.ready.eq(cmd_fifo.sink.ready),
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port_to.valid.eq(cmd_fifo.source.valid),
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port_to.we.eq(cmd_fifo.source.we),
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port_to.adr.eq(cmd_fifo.source.adr),
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cmd_fifo.source.ready.eq(port_to.ready)
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]
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wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 4)
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wdata_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(wdata_fifo)
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self.submodules += wdata_fifo
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self.comb += [
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wdata_fifo.sink.valid.eq(port_from.wdata_valid),
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wdata_fifo.sink.data.eq(port_from.wdata),
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wdata_fifo.sink.we.eq(port_from.wdata_we),
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port_from.wdata_ready.eq(wdata_fifo.sink.ready),
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port_to.wdata_valid.eq(wdata_fifo.source.valid),
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port_to.wdata.eq(wdata_fifo.source.data),
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port_to.wdata_we.eq(wdata_fifo.source.we),
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wdata_fifo.source.ready.eq(port_to.wdata_ready)
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]
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rdata_fifo = stream.AsyncFIFO([("data", dw)], 4)
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rdata_fifo = ClockDomainsRenamer({"write": cd_to, "read": cd_from})(rdata_fifo)
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self.submodules += rdata_fifo
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self.comb += [
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rdata_fifo.sink.valid.eq(port_to.rdata_valid),
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rdata_fifo.sink.data.eq(port_to.rdata),
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port_to.rdata_ready.eq(rdata_fifo.sink.ready),
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port_from.rdata_valid.eq(rdata_fifo.source.valid),
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port_from.rdata.eq(rdata_fifo.source.data),
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rdata_fifo.source.ready.eq(port_from.rdata_ready)
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]
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class LiteDRAMCrossbar(Module):
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def __init__(self, controller, cba_shift):
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@ -23,13 +77,17 @@ class LiteDRAMCrossbar(Module):
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self.masters = []
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def get_port(self):
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def get_port(self, cd="sys"):
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if self.finalized:
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raise FinalizeError
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port = LiteDRAMPort(self.rca_bits + self.bank_bits,
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self.dw)
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self.masters.append(port)
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return port
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port_to = LiteDRAMPort(self.rca_bits + self.bank_bits, self.dw, "sys")
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self.masters.append(port_to)
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if cd != "sys":
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port_from = LiteDRAMPort(self.rca_bits + self.bank_bits, self.dw, cd)
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self.submodules += LiteDRAMAsyncAdapter(port_from, port_to)
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return port_from
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else:
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return port_to
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def do_finalize(self):
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nmasters = len(self.masters)
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@ -43,6 +43,7 @@ class LiteDRAMDMAReader(Module):
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self.comb += [
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fifo.sink.data.eq(port.rdata),
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fifo.sink.valid.eq(port.rdata_valid),
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port.rdata_ready.eq(fifo.sink.ready),
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fifo.source.connect(source),
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data_dequeued.eq(source.valid & source.ready)
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@ -69,6 +70,7 @@ class LiteDRAMDMAWriter(Module):
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]
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self.comb += [
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port.wdata_valid.eq(fifo.source.valid),
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fifo.source.ready.eq(port.wdata_ready),
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port.wdata_we.eq(2**(port.dw//8)-1),
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port.wdata.eq(fifo.source.data)
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@ -8,8 +8,8 @@ from litedram.frontend.bist import LiteDRAMBISTChecker
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class TB(Module):
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def __init__(self):
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self.write_port = LiteDRAMPort(aw=32, dw=32)
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self.read_port = LiteDRAMPort(aw=32, dw=32)
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self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
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self.read_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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