modules: add MT40A1G8 DDR4

2018-11-13 11:05:38 +01:00 · 2018-11-13 11:05:38 +01:00 · 30d9a3e2c2
parent 4459bd25ed
commit 30d9a3e2c2
1 changed files with 14 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -352,3 +352,17 @@ class EDY4016A(SDRAMModule):
        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=260, tFAW=(28, 30), tRAS=32),
    }
    speedgrade_timings["default"] = speedgrade_timings["2400"]
+
+
+class MT40A1G8(SDRAMModule):
+    memtype = "DDR4"
+    # geometry
+    nbanks = 4*4 # 4 groups of 4 banks
+    nrows  = 65536
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9))
+    speedgrade_timings = {
+        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=350, tFAW=(20, 25), tRAS=32),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2400"]