Merge pull request #277 from antmicro/acom/s7phy_ddr4
phy: s7: add DDR4 memtype as well
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commit
3202bc6acd
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@ -36,13 +36,16 @@ class S7DDRPHY(Module, AutoCSR):
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cmd_latency = 0,
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cmd_latency = 0,
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cmd_delay = None,
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cmd_delay = None,
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ddr_clk = None,
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ddr_clk = None,
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csr_cdc = None):
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csr_cdc = None,
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assert memtype in ["DDR2", "DDR3"]
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is_rdimm = False):
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assert memtype in ["DDR2", "DDR3", "DDR4"]
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assert not (memtype == "DDR3" and nphases == 2)
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assert not (memtype == "DDR3" and nphases == 2)
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phytype = self.__class__.__name__
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phytype = self.__class__.__name__
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pads = PHYPadsCombiner(pads)
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pads = PHYPadsCombiner(pads)
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tck = 2/(2*nphases*sys_clk_freq)
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tck = 2/(2*nphases*sys_clk_freq)
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addressbits = len(pads.a)
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addressbits = len(pads.a)
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if memtype == "DDR4":
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addressbits += 3 # cas_n/ras_n/we_n multiplexed with address
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bankbits = len(pads.ba)
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bankbits = len(pads.ba)
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nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
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nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
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databits = len(pads.dq)
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databits = len(pads.dq)
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@ -145,8 +148,20 @@ class S7DDRPHY(Module, AutoCSR):
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bitslips = 8,
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bitslips = 8,
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)
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)
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if is_rdimm:
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# All drive settings for an 8-chip load
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self.settings.set_rdimm(
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tck = tck,
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rcd_pll_bypass = False,
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rcd_ca_cs_drive = 0x5,
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rcd_odt_cke_drive = 0x5,
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rcd_clk_drive = 0x5
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)
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# DFI Interface ----------------------------------------------------------------------------
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# DFI Interface ----------------------------------------------------------------------------
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self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, 4)
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self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
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if memtype == "DDR4":
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self.submodules += DDR4DFIMux(self.dfi, dfi)
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# # #
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# # #
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@ -317,9 +332,12 @@ class S7DDRPHY(Module, AutoCSR):
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# DM ---------------------------------------------------------------------------------------
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# DM ---------------------------------------------------------------------------------------
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if hasattr(pads, "dm"):
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if hasattr(pads, "dm"):
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for i in range(databits//8):
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for i in range(databits//8):
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dm_i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)])
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if memtype == "DDR4": # Inverted polarity for DDR4
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dm_i = ~dm_i
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dm_o_nodelay = Signal()
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dm_o_nodelay = Signal()
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dm_o_bitslip = BitSlip(8,
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dm_o_bitslip = BitSlip(8,
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i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
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i = dm_i,
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rst = (self._dly_sel.storage[i] & wdly_dq_bitslip_rst) | self._rst.storage,
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rst = (self._dly_sel.storage[i] & wdly_dq_bitslip_rst) | self._rst.storage,
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slp = self._dly_sel.storage[i] & wdly_dq_bitslip,
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slp = self._dly_sel.storage[i] & wdly_dq_bitslip,
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cycles = 1)
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cycles = 1)
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