test: add upconverter_tb and some fixes

litedram/frontend/crossbar.py

@@ -164,10 +164,13 @@ class _LiteDRAMUpConverter(Module):
         )
         fsm.act("RECEIVE",
             port_from.cmd.ready.eq(1),
+            If(port_from.cmd.valid,
+                counter_ce.eq(1),
                 If(counter == ratio-1,
                     NextState("GENERATE")
                 )
             )
+        )
         fsm.act("GENERATE",
             port_to.cmd.valid.eq(1),
             port_to.cmd.we.eq(we),
@@ -212,6 +215,7 @@ class LiteDRAMConverter(Module):
                 port_to.rdata.connect(port_from.rdata)
             ]
 
+
 class LiteDRAMCrossbar(Module):
     def __init__(self, controller, cba_shift):
         self.controller = controller

test/Makefile

@@ -12,4 +12,7 @@ bist_async_tb:
 downconverter_tb:
 	$(CMD) downconverter_tb.py
 
-all: bist_tb bist_async_tb downconverter_tb
+upconverter_tb:
+	$(CMD) upconverter_tb.py
+
+all: bist_tb bist_async_tb downconverter_tb upconverter_tb

test/upconverter_tb.py

@@ -0,0 +1,48 @@
+from litex.gen import *
+
+from litex.soc.interconnect.stream import *
+
+from litedram.common import LiteDRAMPort
+from litedram.frontend.crossbar import LiteDRAMConverter
+
+from test.common import DRAMMemory
+
+class TB(Module):
+    def __init__(self):
+        self.user_port = LiteDRAMPort(aw=32, dw=32)
+        self.internal_port = LiteDRAMPort(aw=32, dw=64)
+        self.submodules.converter = LiteDRAMConverter(self.user_port, self.internal_port)
+        self.memory = DRAMMemory(64, 128)
+
+def main_generator(dut):
+    for i in range(8):
+        yield
+    # write
+    for i in range(8):
+        yield dut.user_port.cmd.valid.eq(1)
+        yield dut.user_port.cmd.we.eq(1)
+        yield dut.user_port.cmd.adr.eq(i)
+        yield
+        while (yield dut.user_port.cmd.ready) == 0:
+            yield
+        yield dut.user_port.cmd.valid.eq(0)
+        yield
+        yield dut.user_port.wdata.valid.eq(1)
+        if i%2:
+            yield dut.user_port.wdata.data.eq(0x01234567)
+        else:
+            yield dut.user_port.wdata.data.eq(0x89abcdef)        
+        yield
+        while (yield dut.user_port.wdata.ready) == 0:
+            yield
+        yield dut.user_port.wdata.valid.eq(0)
+        yield
+
+if __name__ == "__main__":
+    tb = TB()
+    generators = {
+        "sys" :   [main_generator(tb),
+                   tb.memory.write_generator(tb.internal_port)]
+    }
+    clocks = {"sys": 10}
+    run_simulation(tb, generators, clocks, vcd_name="sim.vcd")