core/multiplexer: fix rank_decoder width
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@ -105,7 +105,7 @@ class _Steerer(Module):
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# FIXME: add dynamic drive for multi-rank (will be needed for high frequencies)
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self.comb += phase.odt.eq(Replicate(Signal(reset=1), nranks))
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if rankbits:
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rank_decoder = Decoder(rankbits)
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rank_decoder = Decoder(nranks)
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self.submodules += rank_decoder
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self.comb += rank_decoder.i.eq((Array(cmd.ba[-rankbits:] for cmd in commands)[sel]))
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self.sync += phase.cs_n.eq(~rank_decoder.o)
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