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frontend/wishbone: add write data buffer to avoid stalling wishbone while waiting for wdata.ready

This commit is contained in:
Florent Kermarrec 2020-01-10 14:27:05 +01:00
parent 1d2bc922b8
commit 34e6c24d72
1 changed files with 12 additions and 4 deletions
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16
litedram/frontend/wishbone.py
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@ -5,6 +5,9 @@
from migen import * from migen import *
from litex.soc.interconnect import stream
# LiteDRAMWishbone2Native -------------------------------------------------------------------------- # LiteDRAMWishbone2Native --------------------------------------------------------------------------
class LiteDRAMWishbone2Native(Module): class LiteDRAMWishbone2Native(Module):
@ -15,6 +18,10 @@ class LiteDRAMWishbone2Native(Module):
adr_offset = base_address >> log2_int(port.data_width//8) adr_offset = base_address >> log2_int(port.data_width//8)
# Write data buffer-------------------------------------------------------------------------
wdata_buffer = stream.Buffer([("data", port.data_width), ("we", port.data_width//8)])
self.submodules += wdata_buffer
# Control ---------------------------------------------------------------------------------- # Control ----------------------------------------------------------------------------------
self.submodules.fsm = fsm = FSM(reset_state="CMD") self.submodules.fsm = fsm = FSM(reset_state="CMD")
fsm.act("CMD", fsm.act("CMD",
@ -29,8 +36,8 @@ class LiteDRAMWishbone2Native(Module):
) )
) )
fsm.act("WRITE", fsm.act("WRITE",
port.wdata.valid.eq(1), wdata_buffer.sink.valid.eq(1),
If(port.wdata.ready, If(wdata_buffer.sink.ready,
wishbone.ack.eq(1), wishbone.ack.eq(1),
NextState("CMD") NextState("CMD")
) )
@ -48,8 +55,9 @@ class LiteDRAMWishbone2Native(Module):
# Cmd # Cmd
port.cmd.addr.eq(wishbone.adr - adr_offset), port.cmd.addr.eq(wishbone.adr - adr_offset),
# Write # Write
port.wdata.we.eq(wishbone.sel), wdata_buffer.sink.data.eq(wishbone.dat_w),
port.wdata.data.eq(wishbone.dat_w), wdata_buffer.sink.we.eq(wishbone.sel),
wdata_buffer.source.connect(port.wdata),
# Read # Read
wishbone.dat_r.eq(port.rdata.data), wishbone.dat_r.eq(port.rdata.data),
] ]