Merge pull request #177 from antmicro/jboc/unit-tests-bankmachine
Add litedram.core.bankmachine tests
This commit is contained in:
enjoy-digital
GitHub
commit
36d62d5301
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import math
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import unittest
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from migen import *
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# from litex.soc.interconnect import stream
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from litedram.common import *
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from litedram.core.bankmachine import BankMachine
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from test.common import timeout_generator
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class BankMachineDUT(Module):
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# fill only settings needed by BankMachine
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default_controller_settings = dict(
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cmd_buffer_depth=8,
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cmd_buffer_buffered=False,
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with_auto_precharge=True,
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)
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default_phy_settings = dict(
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cwl=2,
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nphases=2,
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nranks=1,
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# indirectyl
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memtype="DDR2",
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dfi_databits=2*16,
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)
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default_geom_settings = dict(
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bankbits=3,
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rowbits=13,
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colbits=10,
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)
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default_timing_settings = dict(
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tRAS=None,
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tRC=None,
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tCCD=1,
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tRCD=2,
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tRP=2,
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tWR=2,
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)
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def __init__(self, n, controller_settings=None, phy_settings=None, geom_settings=None,
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timing_settings=None):
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# update settings if provided
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def updated(settings, update):
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copy = settings.copy()
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copy.update(update or {})
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return copy
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controller_settings = updated(self.default_controller_settings, controller_settings)
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phy_settings = updated(self.default_phy_settings, phy_settings)
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geom_settings = updated(self.default_geom_settings, geom_settings)
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timing_settings = updated(self.default_timing_settings, timing_settings)
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class SimpleSettings(Settings):
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def __init__(self, **kwargs):
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self.set_attributes(kwargs)
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settings = SimpleSettings(**controller_settings)
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settings.phy = SimpleSettings(**phy_settings)
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settings.geom = SimpleSettings(**geom_settings)
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settings.timing = SimpleSettings(**timing_settings)
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settings.geom.addressbits = max(settings.geom.rowbits, settings.geom.colbits)
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self.settings = settings
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self.address_align = log2_int(burst_lengths[settings.phy.memtype])
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self.address_width = LiteDRAMInterface(self.address_align, settings).address_width
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bankmachine = BankMachine(n=n, address_width=self.address_width,
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address_align=self.address_align,
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nranks=settings.phy.nranks, settings=settings)
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self.submodules.bankmachine = bankmachine
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def get_cmd(self):
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# cmd_request_rw_layout -> name
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layout = [name for name, _ in cmd_request_rw_layout(a=self.settings.geom.addressbits,
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ba=self.settings.geom.bankbits)]
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request = {}
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for name in layout + ["valid", "ready", "first", "last"]:
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request[name] = (yield getattr(self.bankmachine.cmd, name))
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request["type"] = {
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(0, 0, 0): "nop",
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(1, 0, 1): "write",
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(1, 0, 0): "read",
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(0, 1, 0): "activate",
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(0, 1, 1): "precharge",
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(1, 1, 0): "refresh",
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}[(request["cas"], request["ras"], request["we"])]
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return request
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def req_address(self, row, col):
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col = col & (2**self.settings.geom.colbits - 1)
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row = row & (2**self.settings.geom.rowbits - 1)
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split = self.settings.geom.colbits - self.address_align
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return (row << split) | col
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class TestBankMachine(unittest.TestCase):
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def test_init(self):
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BankMachineDUT(1)
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def bankmachine_commands_test(self, dut, requests, generators=None):
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# perform a test by simulating requests producer and return registered commands
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commands = []
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def producer(dut):
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for req in requests:
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yield dut.bankmachine.req.addr.eq(req["addr"])
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yield dut.bankmachine.req.we.eq(req["we"])
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yield dut.bankmachine.req.valid.eq(1)
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yield
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while not (yield dut.bankmachine.req.ready):
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yield
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yield dut.bankmachine.req.valid.eq(0)
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for _ in range(req.get("delay", 0)):
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yield
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def req_consumer(dut):
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for req in requests:
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if req["we"]:
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signal = dut.bankmachine.req.wdata_ready
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else:
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signal = dut.bankmachine.req.rdata_valid
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while not (yield signal):
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yield
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yield
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@passive
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def cmd_consumer(dut):
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while True:
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while not (yield dut.bankmachine.cmd.valid):
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yield
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yield dut.bankmachine.cmd.ready.eq(1)
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yield
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commands.append((yield from dut.get_cmd()))
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yield dut.bankmachine.cmd.ready.eq(0)
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yield
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all_generators = [
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producer(dut),
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req_consumer(dut),
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cmd_consumer(dut),
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timeout_generator(50 * len(requests)),
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]
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if generators is not None:
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all_generators += [g(dut) for g in generators]
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run_simulation(dut, all_generators)
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return commands
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def test_opens_correct_row(self):
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# Verify that the correct row is activated before read/write commands
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dut = BankMachineDUT(3)
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requests = [
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dict(addr=dut.req_address(row=0xf0, col=0x0d), we=0),
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dict(addr=dut.req_address(row=0xd0, col=0x0d), we=1),
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]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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# commands: activate, read (auto-precharge), activate, write
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self.assertEqual(commands[0]["type"], "activate")
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self.assertEqual(commands[0]["a"], 0xf0)
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self.assertEqual(commands[2]["type"], "activate")
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self.assertEqual(commands[2]["a"], 0xd0)
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def test_correct_bank_address(self):
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# Verify that `ba` always corresponds to the BankMachine number
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for bn in [0, 2, 7]:
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with self.subTest(bn=bn):
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dut = BankMachineDUT(bn, geom_settings=dict(bankbits=3))
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requests = [dict(addr=0, we=0)]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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for cmd in commands:
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self.assertEqual(cmd["ba"], bn)
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def test_read_write_same_row(self):
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# Verify that there is only one activate when working on single row
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dut = BankMachineDUT(1)
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=0),
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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dict(addr=dut.req_address(row=0xba, col=0xbe), we=0),
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dict(addr=dut.req_address(row=0xba, col=0xbe), we=1),
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]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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expected = [
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("activate", 0xba),
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("read", 0xad << dut.address_align),
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("write", 0xad << dut.address_align),
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("read", 0xbe << dut.address_align),
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("write", 0xbe << dut.address_align),
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]
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self.assertEqual(commands, expected)
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def test_write_different_rows_with_delay(self):
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# Verify that precharge is used when changing row with a delay
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# this is independent form auto-precharge
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for auto_precharge in [False, True]:
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with self.subTest(auto_precharge=auto_precharge):
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settings = dict(with_auto_precharge=auto_precharge)
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dut = BankMachineDUT(1, controller_settings=settings)
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1, delay=8),
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dict(addr=dut.req_address(row=0xda, col=0xad), we=1),
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]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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expected = [
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("activate", 0xba),
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("write", 0xad << dut.address_align),
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("precharge", 0xad << dut.address_align),
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("activate", 0xda),
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("write", 0xad << dut.address_align),
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]
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self.assertEqual(commands, expected)
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def test_write_different_rows_with_auto_precharge(self):
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# Verify that auto-precharge is used when changing row without delay
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settings = dict(with_auto_precharge=True)
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dut = BankMachineDUT(1, controller_settings=settings)
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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dict(addr=dut.req_address(row=0xda, col=0xad), we=1),
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]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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expected = [
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("activate", 0xba),
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("write", (0xad << dut.address_align) | (1 << 10)),
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("activate", 0xda),
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("write", 0xad << dut.address_align),
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]
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self.assertEqual(commands, expected)
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def test_write_different_rows_without_auto_precharge(self):
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# Verify that auto-precharge is used when changing row without delay
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settings = dict(with_auto_precharge=False)
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dut = BankMachineDUT(1, controller_settings=settings)
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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dict(addr=dut.req_address(row=0xda, col=0xad), we=1),
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]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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expected = [
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("activate", 0xba),
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("write", 0xad << dut.address_align),
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("precharge", 0xad << dut.address_align),
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("activate", 0xda),
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("write", 0xad << dut.address_align),
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]
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self.assertEqual(commands, expected)
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def test_burst_no_request_lost(self):
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# Verify that no request is lost in fast bursts of requests regardless of cmd_buffer_depth
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for cmd_buffer_depth in [8]:
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settings = dict(cmd_buffer_depth=cmd_buffer_depth)
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with self.subTest(**settings):
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dut = BankMachineDUT(1, controller_settings=settings)
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# long sequence of writes to the same row
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requests = [dict(addr=dut.req_address(row=0xba, col=i), we=1) for i in range(32)]
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expected = ([("activate", 0xba)] +
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[("write", i << dut.address_align) for i in range(32)])
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commands = self.bankmachine_commands_test(dut=dut, requests=requests)
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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self.assertEqual(commands, expected)
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def test_lock_until_requests_finished(self):
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# Verify that lock is being held until all requests in FIFO are processed
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@passive
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def lock_checker(dut):
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req = dut.bankmachine.req
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self.assertEqual((yield req.lock), 0)
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# wait until first request becomes locked
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while not (yield req.valid):
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yield
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# wait until lock should be released (all requests in queue gets processed)
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# here it happens when the final wdata_ready ends
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for _ in range(3):
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while not (yield req.wdata_ready):
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yield
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self.assertEqual((yield req.lock), 1)
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yield
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yield
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self.assertEqual((yield req.lock), 0)
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dut = BankMachineDUT(1)
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# simple sequence with row change
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requests = [
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dict(addr=dut.req_address(row=0x1a, col=0x01), we=1),
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dict(addr=dut.req_address(row=0x1b, col=0x02), we=1),
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dict(addr=dut.req_address(row=0x1c, col=0x04), we=1),
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]
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self.bankmachine_commands_test(dut=dut, requests=requests, generators=[lock_checker])
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def timing_test(self, from_cmd, to_cmd, time_expected, **dut_kwargs):
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@passive
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def timing_checker(dut):
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def is_cmd(cmd_type, test_ready):
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cmd = (yield from dut.get_cmd())
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ready = cmd["ready"] if test_ready else True
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return cmd["valid"] and ready and cmd["type"] == cmd_type
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# time between WRITE ends (ready and valid) and PRECHARGE becomes valid
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while not (yield from is_cmd(from_cmd, test_ready=True)):
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yield
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yield # wait until cmd deactivates in case the second cmd is the same as first
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time = 1
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while not (yield from is_cmd(to_cmd, test_ready=False)):
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yield
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time += 1
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self.assertEqual(time, time_expected)
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dut = BankMachineDUT(1, **dut_kwargs)
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# simple sequence with row change
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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dict(addr=dut.req_address(row=0xda, col=0xad), we=1),
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]
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self.bankmachine_commands_test(dut=dut, requests=requests, generators=[timing_checker])
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def test_timing_write_to_precharge(self):
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controller_settings = dict(with_auto_precharge=False)
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timing_settings = dict(tWR=6, tCCD=4)
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phy_settings = dict(cwl=2, nphases=2)
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write_latency = math.ceil(phy_settings["cwl"] / phy_settings["nphases"])
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precharge_time = write_latency + timing_settings["tWR"] + timing_settings["tCCD"]
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self.timing_test("write", "precharge", precharge_time,
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controller_settings=controller_settings,
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phy_settings=phy_settings,
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timing_settings=timing_settings)
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def test_timing_activate_to_activate(self):
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timing_settings = dict(tRC=16)
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self.timing_test("activate", "activate", time_expected=16,
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timing_settings=timing_settings)
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def test_timing_activate_to_precharge(self):
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timing_settings = dict(tRAS=32)
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self.timing_test("activate", "precharge", time_expected=32,
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timing_settings=timing_settings)
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def test_refresh(self):
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# Verify that no commands are issued during refresh and after it the row is re-activated
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@passive
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def refresh_generator(dut):
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# wait some time for the bankmachine to start
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for _ in range(16):
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yield
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# request a refresh
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yield dut.bankmachine.refresh_req.eq(1)
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while not (yield dut.bankmachine.refresh_gnt):
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yield
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# wait when refresh is being performed
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# make sure no command is issued during refresh
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for _ in range(32):
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self.assertEqual((yield dut.bankmachine.cmd.valid), 0)
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yield
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# signalize refresh is ready
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yield dut.bankmachine.refresh_req.eq(0)
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dut = BankMachineDUT(1)
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requests = [dict(addr=dut.req_address(row=0xba, col=i), we=1) for i in range(16)]
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commands = self.bankmachine_commands_test(dut=dut, requests=requests,
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generators=[refresh_generator])
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commands = [(cmd["type"], cmd["a"]) for cmd in commands]
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# refresh will close row, so bankmachine should re-activate it after refresh
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self.assertEqual(commands.count(("activate", 0xba)), 2)
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# verify that the write commands are correct
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write_commands = [cmd for cmd in commands if cmd[0] == "write"]
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expected_writes = [("write", i << dut.address_align) for i in range(16)]
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self.assertEqual(write_commands, expected_writes)
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def test_output_annotations(self):
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# Verify that all commands are annotated correctly using is_* signals
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checked = set()
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@passive
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def cmd_checker(dut):
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while True:
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cmd = (yield from dut.get_cmd())
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if cmd["valid"]:
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if cmd["type"] in ["activate", "precharge"]:
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self.assertEqual(cmd["is_cmd"], 1)
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self.assertEqual(cmd["is_write"], 0)
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self.assertEqual(cmd["is_read"], 0)
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elif cmd["type"] in ["write"]:
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self.assertEqual(cmd["is_cmd"], 0)
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self.assertEqual(cmd["is_write"], 1)
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self.assertEqual(cmd["is_read"], 0)
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elif cmd["type"] in ["read"]:
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self.assertEqual(cmd["is_cmd"], 0)
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self.assertEqual(cmd["is_write"], 0)
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self.assertEqual(cmd["is_read"], 1)
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else:
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raise ValueError(cmd["type"])
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checked.add(cmd["type"])
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yield
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dut = BankMachineDUT(1)
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requests = [
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dict(addr=dut.req_address(row=0xba, col=0xad), we=0),
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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dict(addr=dut.req_address(row=0xda, col=0xad), we=0),
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# wait enough time for regular (not auto) precharge to be used
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dict(addr=dut.req_address(row=0xda, col=0xad), we=1, delay=32),
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dict(addr=dut.req_address(row=0xba, col=0xad), we=0),
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dict(addr=dut.req_address(row=0xba, col=0xad), we=1),
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]
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self.bankmachine_commands_test(dut=dut, requests=requests, generators=[cmd_checker])
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# bankmachine does not produce refresh commands
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self.assertEqual(checked, {"activate", "precharge", "write", "read"})
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