init: add helper class to make C code generation simpler
This commit is contained in:
Jędrzej Boczar
parent
2200bd43a5
commit
377746bfd8
274
litedram/init.py
274
litedram/init.py
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@ -11,6 +11,7 @@
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# SPDX-License-Identifier: BSD-2-Clause
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import math
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from contextlib import contextmanager
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from migen import *
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@ -643,147 +644,219 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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# C Header -----------------------------------------------------------------------------------------
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class CGenerator(list):
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# C code generator - list of strings (=lines) or CGenerator instances (sub-generators)
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def __init__(self, indent=0, indent_str="\t"):
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self.indent = indent
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self.indent_str = indent_str
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def __iadd__(self, x):
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# make `c += "int x = 0;"` append it as line, not char-by-char
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if isinstance(x, str):
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x = [x]
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return super().__iadd__(x)
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def header_guard(self, name):
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self._header_guard = name
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def generate_lines(self):
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if getattr(self, "_header_guard", None) is not None:
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self.insert(0, f"#ifndef {self._header_guard}")
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self.insert(1, f"#define {self._header_guard}")
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self.insert(2, "")
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self.append("")
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self.append(f"#endif /* {self._header_guard} */")
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self._header_guard = None
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lines = []
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for entry in self:
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if isinstance(entry, CGenerator):
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lines.extend(entry.generate_lines())
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else:
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line = (self.indent * self.indent_str) + entry
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lines.append(line.rstrip())
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return lines
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def generate(self):
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lines = self.generate_lines()
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return "\n".join(lines).strip() + "\n"
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def include(self, path):
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self.append(f"#include {path}")
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def define(self, var, value=None):
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if isinstance(value, (int, float)):
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value = str(value)
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self.append(f"#define {var}" + (f" {value}" if value is not None else ""))
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def newline(self, n=1):
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self.extend([""] * n)
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@contextmanager
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def block(self, head=None, newline=True):
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if head is not None:
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self.append(head + (" {" if not newline else ""))
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if newline:
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self.append("{")
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else:
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self.append("{")
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subgenerator = CGenerator(indent=self.indent + 1, indent_str=self.indent_str)
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yield subgenerator
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self.append(subgenerator)
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self.append("}")
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def get_sdram_phy_c_header(phy_settings, timing_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n"
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r += "#include <generated/csr.h>\n"
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r += "\n"
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r = CGenerator()
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r.header_guard("__GENERATED_SDRAM_PHY_H")
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r.include("<hw/common.h>")
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r.include("<generated/csr.h>")
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r.newline()
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r += "#define DFII_CONTROL_SEL 0x01\n"
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r += "#define DFII_CONTROL_CKE 0x02\n"
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r += "#define DFII_CONTROL_ODT 0x04\n"
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r += "#define DFII_CONTROL_RESET_N 0x08\n"
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r += "\n"
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r.define("DFII_CONTROL_SEL", "0x01")
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r.define("DFII_CONTROL_CKE", "0x02")
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r.define("DFII_CONTROL_ODT", "0x04")
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r.define("DFII_CONTROL_RESET_N", "0x08")
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r.newline()
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r += "#define DFII_COMMAND_CS 0x01\n"
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r += "#define DFII_COMMAND_WE 0x02\n"
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r += "#define DFII_COMMAND_CAS 0x04\n"
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r += "#define DFII_COMMAND_RAS 0x08\n"
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r += "#define DFII_COMMAND_WRDATA 0x10\n"
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r += "#define DFII_COMMAND_RDDATA 0x20\n"
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r += "\n"
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r.define("DFII_COMMAND_CS", "0x01")
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r.define("DFII_COMMAND_WE", "0x02")
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r.define("DFII_COMMAND_CAS", "0x04")
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r.define("DFII_COMMAND_RAS", "0x08")
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r.define("DFII_COMMAND_WRDATA", "0x10")
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r.define("DFII_COMMAND_RDDATA", "0x20")
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r.newline()
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phytype = phy_settings.phytype.upper()
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nphases = phy_settings.nphases
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# Define PHY type and number of phases
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r += "#define SDRAM_PHY_"+phytype+"\n"
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r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n"
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r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n"
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r += "#define SDRAM_PHY_DFI_DATABITS "+str(phy_settings.dfi_databits) + "\n"
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r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n"
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if phy_settings.cl is not None:
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r += "#define SDRAM_PHY_CL "+str(phy_settings.cl)+"\n"
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if phy_settings.cwl is not None:
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r += "#define SDRAM_PHY_CWL "+str(phy_settings.cwl)+"\n"
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if phy_settings.cmd_latency is not None:
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r += "#define SDRAM_PHY_CMD_LATENCY "+str(phy_settings.cmd_latency)+"\n"
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if phy_settings.cmd_delay is not None:
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r += "#define SDRAM_PHY_CMD_DELAY "+str(phy_settings.cmd_delay)+"\n"
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r.define(f"SDRAM_PHY_{phytype}")
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r.define("SDRAM_PHY_XDR", 1 if phy_settings.memtype == "SDR" else 2)
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r.define("SDRAM_PHY_DATABITS", phy_settings.databits)
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r.define("SDRAM_PHY_DFI_DATABITS", phy_settings.dfi_databits)
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r.define("SDRAM_PHY_PHASES", nphases)
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for setting in ["cl", "cwl", "cmd_latency", "cmd_delay"]:
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if getattr(phy_settings, setting, None) is not None:
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r.define(f"SDRAM_PHY_{setting.upper()}", getattr(phy_settings, setting))
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# Define PHY Read.Write phases
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rdphase = phy_settings.rdphase
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if isinstance(rdphase, Signal): rdphase = rdphase.reset.value
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r += "#define SDRAM_PHY_RDPHASE "+str(rdphase)+"\n"
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r.define("SDRAM_PHY_RDPHASE", rdphase)
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wrphase = phy_settings.wrphase
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if isinstance(wrphase, Signal): wrphase = wrphase.reset.value
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r += "#define SDRAM_PHY_WRPHASE "+str(wrphase)+"\n"
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r.define("SDRAM_PHY_WRPHASE", wrphase)
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# Define Read/Write Leveling capability
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phy_settings.write_leveling = False
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phy_settings.write_dq_dqs_training = False
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phy_settings.write_latency_calibration = False
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phy_settings.read_leveling = False
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if phytype in ["USDDRPHY", "USPDDRPHY",
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"K7DDRPHY", "V7DDRPHY",
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"K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
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phy_settings.write_leveling = True
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if phytype in ["K7DDRPHY", "V7DDRPHY",
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"K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
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phy_settings.write_dq_dqs_training = True
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if phytype in ["USDDRPHY", "USPDDRPHY",
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"A7DDRPHY", "K7DDRPHY", "V7DDRPHY",
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"A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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phy_settings.write_latency_calibration = True
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phy_settings.read_leveling = True
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if phytype in ["ECP5DDRPHY"]:
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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phy_settings.read_leveling = True
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if phytype in ["LPDDR4SIMPHY"]:
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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phy_settings.read_leveling = True
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phy_settings.delays = None
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phy_settings.bitslips = None
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if phytype in ["USDDRPHY", "USPDDRPHY"]:
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phy_settings.delays = 512
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phy_settings.bitslips = 8
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elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
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phy_settings.delays = 32
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phy_settings.bitslips = 8
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elif phytype in ["A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
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phy_settings.delays = 32
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phy_settings.bitslips = 16
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elif phytype in ["ECP5DDRPHY"]:
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phy_settings.delays = 8
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phy_settings.bitslips = 4
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elif phytype in ["LPDDR4SIMPHY"]:
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phy_settings.delays = 1
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phy_settings.bitslips = 16
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# Define Read/Write Leveling capability
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if phy_settings.write_leveling:
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r.define("SDRAM_PHY_WRITE_LEVELING_CAPABLE")
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if phy_settings.write_latency_calibration:
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r.define("SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE")
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if phy_settings.write_dq_dqs_training:
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r.define("SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE")
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if phy_settings.read_leveling:
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r.define("SDRAM_PHY_READ_LEVELING_CAPABLE")
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# Define number of modules/delays/bitslips
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r += "#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)\n"
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r.define("SDRAM_PHY_MODULES", "(SDRAM_PHY_DATABITS/8)")
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if phytype in ["USDDRPHY", "USPDDRPHY"]:
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r += "#define SDRAM_PHY_DELAYS 512\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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r.define("SDRAM_PHY_DELAYS", 512)
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r.define("SDRAM_PHY_BITSLIPS", 8)
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elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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r.define("SDRAM_PHY_DELAYS", 32)
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r.define("SDRAM_PHY_BITSLIPS", 8)
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elif phytype in ["A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 16\n"
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r.define("SDRAM_PHY_DELAYS", 32)
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r.define("SDRAM_PHY_BITSLIPS", 16)
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elif phytype in ["ECP5DDRPHY"]:
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r += "#define SDRAM_PHY_DELAYS 8\n"
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r += "#define SDRAM_PHY_BITSLIPS 4\n"
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r.define("SDRAM_PHY_DELAYS", 8)
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r.define("SDRAM_PHY_BITSLIPS", 4)
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elif phytype in ["LPDDR4SIMPHY"]:
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r += "#define SDRAM_PHY_DELAYS 1\n"
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r += "#define SDRAM_PHY_BITSLIPS 16\n"
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r.define("SDRAM_PHY_DELAYS", 1)
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r.define("SDRAM_PHY_BITSLIPS", 16)
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if phy_settings.is_rdimm:
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assert phy_settings.memtype == "DDR4"
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r += "#define SDRAM_PHY_DDR4_RDIMM\n"
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r.define("SDRAM_PHY_DDR4_RDIMM")
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r += "\n"
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r.newline()
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r += "void cdelay(int i);\n"
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r += "void cdelay(int i);"
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r.newline()
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# Commands functions
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for n in range(nphases):
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r += """
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__attribute__((unused)) static inline void command_p{n}(int cmd)
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{{
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sdram_dfii_pi{n}_command_write(cmd);
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sdram_dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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with r.block(f"__attribute__((unused)) static inline void command_p{n}(int cmd)") as b:
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b += f"sdram_dfii_pi{n}_command_write(cmd);"
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b += f"sdram_dfii_pi{n}_command_issue_write(1);"
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r.newline()
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# Write/Read functions
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pix_addr_fmt = """
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static inline unsigned long {name}(int phase){{
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switch (phase) {{
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{cases}
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default: return 0;
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}}
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}}
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"""
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get_cases = lambda addrs: ["case {}: return {};".format(i, addr) for i, addr in enumerate(addrs)]
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r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
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sdram_dfii_pix_wrdata_addr = []
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r.define("DFII_PIX_DATA_SIZE", "CSR_SDRAM_DFII_PI0_WRDATA_SIZE")
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r.newline()
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for data in ["wrdata", "rddata"]:
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with r.block(f"static inline unsigned long sdram_dfii_pix_{data}_addr(int phase)") as b:
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with b.block("switch (phase)", newline=False) as s:
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for n in range(nphases):
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sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
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r += pix_addr_fmt.format(
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name = "sdram_dfii_pix_wrdata_addr",
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cases = "\n\t\t".join(get_cases(sdram_dfii_pix_wrdata_addr)))
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sdram_dfii_pix_rddata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
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r += pix_addr_fmt.format(
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name = "sdram_dfii_pix_rddata_addr",
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cases = "\n\t\t".join(get_cases(sdram_dfii_pix_rddata_addr)))
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r += "\n"
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s += f"case {n}: return CSR_SDRAM_DFII_PI{n}_{data.upper()}_ADDR;"
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s += "default: return 0;"
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r.newline()
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init_sequence, mr = get_sdram_phy_init_sequence(phy_settings, timing_settings)
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if phy_settings.memtype in ["DDR3", "DDR4"]:
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# The value of MR1[7] needs to be modified during write leveling
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r += "#define DDRX_MR_WRLVL_ADDRESS {}\n".format(1)
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r += "#define DDRX_MR_WRLVL_RESET {}\n".format(mr[1])
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r += "#define DDRX_MR_WRLVL_BIT {}\n\n".format(7)
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r.define("DDRX_MR_WRLVL_ADDRESS", 1)
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r.define("DDRX_MR_WRLVL_RESET", mr[1])
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r.define("DDRX_MR_WRLVL_BIT", 7)
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r.newline()
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elif phy_settings.memtype in ["LPDDR4"]:
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# Write leveling enabled by MR2[7]
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r += "#define DDRX_MR_WRLVL_ADDRESS {}\n".format(2)
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r += "#define DDRX_MR_WRLVL_RESET {}\n".format(mr[2])
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r += "#define DDRX_MR_WRLVL_BIT {}\n\n".format(7)
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r.define("DDRX_MR_WRLVL_ADDRESS", 2)
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r.define("DDRX_MR_WRLVL_RESET", mr[2])
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r.define("DDRX_MR_WRLVL_BIT", 7)
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r.newline()
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r += "static inline void init_sequence(void)\n{\n"
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with r.block("static inline void init_sequence(void)") as b:
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for comment, a, ba, cmd, delay in init_sequence:
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invert_masks = [(0, 0), ]
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if phy_settings.is_rdimm:
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@ -801,21 +874,18 @@ static inline unsigned long {name}(int phase){{
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invert_masks.append((0b10101111111000, 0b1111))
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for a_inv, ba_inv in invert_masks:
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r += "\t/* {0} */\n".format(comment)
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r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a ^ a_inv)
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r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba ^ ba_inv)
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if cmd[:12] == "DFII_CONTROL":
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r += "\tsdram_dfii_control_write({0});\n".format(cmd)
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b += f"/* {comment} */"
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b += f"sdram_dfii_pi0_address_write({a ^ a_inv:#x});"
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b += f"sdram_dfii_pi0_baddress_write({ba ^ ba_inv:d});"
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if cmd.startswith("DFII_CONTROL"):
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b += f"sdram_dfii_control_write({cmd});"
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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b += f"command_p0({cmd});"
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if delay:
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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r += "}\n"
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b += f"cdelay({delay});\n"
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b.newline()
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r += "#endif\n"
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return r
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return r.generate()
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# Python Header ------------------------------------------------------------------------------------
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