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frontend/bist: rename run/ready to run_cascade_in/run_cascade_out.

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This commit is contained in:
Florent Kermarrec 2020-04-14 16:52:02 +02:00
parent 829dee6a61
commit 378c4419c1
2 changed files with 31 additions and 24 deletions
litedram/frontend
bist.py
test
benchmark.py

50
litedram/frontend/bist.py
View file

@ -133,8 +133,6 @@ class _LiteDRAMBISTGenerator(Module):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.run = Signal(reset=1)
self.ready = Signal()
self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth)
@ -142,6 +140,9 @@ class _LiteDRAMBISTGenerator(Module):
self.random_addr = Signal()
self.ticks = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address generators ----------------------------------------------------------------
@ -172,27 +173,27 @@ class _LiteDRAMBISTGenerator(Module):
NextValue(self.ticks, 0)
)
fsm.act("WAIT",
If(self.run,
If(self.run_cascade_in,
NextState("RUN")
)
)
fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.ready.eq(1),
self.run_cascade_out.eq(1),
data_gen.ce.eq(1),
addr_gen.ce.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (self.length[ashift:] - 1),
NextState("DONE")
).Elif(~self.run,
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
),
NextValue(self.ticks, self.ticks + 1)
)
fsm.act("DONE",
self.ready.eq(1),
self.run_cascade_out.eq(1),
self.done.eq(1)
)
@ -213,10 +214,11 @@ class _LiteDRAMPatternGenerator(Module):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.run = Signal(reset=1)
self.ready = Signal()
self.ticks = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address pattern -------------------------------------------------------------------
@ -244,25 +246,25 @@ class _LiteDRAMPatternGenerator(Module):
NextValue(self.ticks, 0)
)
fsm.act("WAIT",
If(self.run,
If(self.run_cascade_in,
NextState("RUN")
)
)
fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.ready.eq(1),
self.run_cascade_out.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (len(init) - 1),
NextState("DONE")
).Elif(~self.run,
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
),
NextValue(self.ticks, self.ticks + 1)
)
fsm.act("DONE",
self.ready.eq(1),
self.run_cascade_out.eq(1),
self.done.eq(1)
)
@ -402,8 +404,6 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.run = Signal(reset=1)
self.ready = Signal()
self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth)
@ -412,6 +412,9 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.ticks = Signal(32)
self.errors = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address generators ----------------------------------------------------------------
@ -441,19 +444,19 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
)
)
cmd_fsm.act("WAIT",
If(self.run,
If(self.run_cascade_in,
NextState("RUN")
)
)
cmd_fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.ready.eq(1),
self.run_cascade_out.eq(1),
addr_gen.ce.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (self.length[ashift:] - 1),
NextState("DONE")
).Elif(~self.run,
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
)
@ -507,11 +510,12 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.run = Signal(reset=1)
self.ready = Signal()
self.ticks = Signal(32)
self.errors = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address pattern -------------------------------------------------------------------
@ -534,7 +538,7 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
cmd_fsm.act("IDLE",
If(self.start,
NextValue(cmd_counter, 0),
If(self.run,
If(self.run_cascade_in,
NextState("RUN")
).Else(
NextState("WAIT")
@ -542,7 +546,7 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
)
)
cmd_fsm.act("WAIT",
If(self.run,
If(self.run_cascade_in,
NextState("RUN")
),
NextValue(self.ticks, self.ticks + 1)
@ -550,11 +554,11 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
cmd_fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.ready.eq(1),
self.run_cascade_out.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (len(init) - 1),
NextState("DONE")
).Elif(~self.run,
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
)

5
test/benchmark.py
View file

@ -127,7 +127,10 @@ class LiteDRAMBenchmarkSoC(SimSoC):
for generator, checker in zip_longest(generators, checkers):
g = generator or generators[0]
c = checker or checkers[0]
bist_connections += g.run.eq(c.ready), c.run.eq(g.ready)
bist_connections += [
g.run_cascade_in.eq(c.run_cascade_out),
c.run_cascade_in.eq(g.run_cascade_out),
]
fsm.act("BIST-GENERATOR",
combined_write(generators + checkers, "start").eq(1),