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phy/kusddrphy: reset bitslip on wdly_dq_rst instead of rdly_dq_rst

This commit is contained in:
Florent Kermarrec 2017-11-08 21:52:56 +01:00
parent f31f8a03ff
commit 38f1c268e9
1 changed files with 1 additions and 1 deletions
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litedram/phy/kusddrphy.py
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@ -200,7 +200,7 @@ class KUSDDRPHY(Module, AutoCSR):
dq_bitslip = BitSlip(8) dq_bitslip = BitSlip(8)
self.sync += \ self.sync += \
If(self._dly_sel.storage[i//8], If(self._dly_sel.storage[i//8],
If(self._rdly_dq_rst.re, If(self._wdly_dq_rst.re,
dq_bitslip.value.eq(0) dq_bitslip.value.eq(0)
).Elif(self._rdly_dq_bitslip.re, ).Elif(self._rdly_dq_bitslip.re,
dq_bitslip.value.eq(dq_bitslip.value + 1) dq_bitslip.value.eq(dq_bitslip.value + 1)