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phy/s6ddrphy: use cwl only for DDR3

This commit is contained in:
Florent Kermarrec 2018-08-27 13:23:29 +02:00
parent d9b5bb7247
commit 3fa77c8417
1 changed files with 4 additions and 1 deletions
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3
litedram/phy/s6ddrphy.py
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@ -375,7 +375,10 @@ class S6HalfRateDDRPHY(Module):
wrdata_en_d = Signal() wrdata_en_d = Signal()
sd_sys += wrdata_en_d.eq(wrdata_en) sd_sys += wrdata_en_d.eq(wrdata_en)
if memtype == "DDR3":
r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl)) r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl))
else:
r_dfi_wrdata_en = Signal(self.settings.cl)
sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en)) sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en))
if memtype == "DDR3": if memtype == "DDR3":