phy/utils: add HoldValid stream primitive
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@ -13,6 +13,7 @@ from collections import defaultdict
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from migen import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.csr import CSRStorage, AutoCSR
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from litedram.common import TappedDelayLine, Settings
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@ -158,16 +159,16 @@ class SimulationPads(Module):
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if pad.io:
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o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
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setattr(self, pad.name, Signal(pad.width))
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setattr(self, o, Signal(pad.width))
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setattr(self, i, Signal(pad.width))
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setattr(self, oe, Signal())
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setattr(self, o, Signal(pad.width, name=o))
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setattr(self, i, Signal(pad.width, name=i))
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setattr(self, oe, Signal(name=oe))
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self.comb += If(getattr(self, oe),
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getattr(self, pad.name).eq(getattr(self, o))
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).Else(
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getattr(self, pad.name).eq(getattr(self, i))
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)
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else:
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setattr(self, pad.name, Signal(pad.width))
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setattr(self, pad.name, Signal(pad.width, name=pad.name))
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class CommandsPipeline(Module):
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@ -411,3 +412,34 @@ class SimLogger(Module, AutoCSR):
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fmt = f"[%16d ps] {fmt}"
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args = (self.time_ps, *args)
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self.sync += If((level >= self.level) & cond, Display(fmt, *args))
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class HoldValid(Module):
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"""Hold input data until ready
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Acts more or less like PipeValid with 0 latency. Data on source becomes valid in the same
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cycle on which it is valid on sink. In the next cycle the data is latched to a buffer and
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the data from buffer is presented on source. After source.ready, it resets back to sink data.
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"""
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def __init__(self, layout):
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self.sink = stream.Endpoint(layout)
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self.buf = stream.Endpoint(layout)
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self.source = stream.Endpoint(layout)
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self.sync += [
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If(self.buf.ready,
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self.buf.valid.eq(0),
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).Elif(self.sink.valid,
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self.buf.valid.eq(1),
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self.buf.payload.eq(self.sink.payload),
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self.buf.param.eq(self.sink.param),
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),
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]
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self.comb += [
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If(self.buf.valid,
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self.buf.connect(self.source),
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).Else(
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self.sink.connect(self.source),
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),
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]
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