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phy/kusddrphy: use specific sys4x_dqs clock since we can't ensure initial delay between dq/dqs using odelaye3 on ultrascale... 

tap delay can vary from 2.5 to 15ps across PVT
This commit is contained in:
Florent Kermarrec 2017-07-10 14:39:54 +02:00
parent 5977a6fca0
commit 40a8504dd6
1 changed files with 1 additions and 4 deletions
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5
litedram/phy/kusddrphy.py
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@ -164,7 +164,7 @@ class KUSDDRPHY(Module, AutoCSR):
o_OQ=dqs_nodelay, o_T_OUT=dqs_t, o_OQ=dqs_nodelay, o_T_OUT=dqs_t,
i_RST=ResetSignal(), i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_CLK=ClockSignal("sys4x_dqs"), i_CLKDIV=ClockSignal(),
i_D=Cat(dqs_serdes_pattern[0], dqs_serdes_pattern[1], i_D=Cat(dqs_serdes_pattern[0], dqs_serdes_pattern[1],
dqs_serdes_pattern[2], dqs_serdes_pattern[3], dqs_serdes_pattern[2], dqs_serdes_pattern[3],
dqs_serdes_pattern[4], dqs_serdes_pattern[5], dqs_serdes_pattern[4], dqs_serdes_pattern[5],
@ -174,9 +174,6 @@ class KUSDDRPHY(Module, AutoCSR):
Instance("ODELAYE3", Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0, p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0, p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
# we should preconfigure delay to 500ps with tCK=5ns but since tap
# size can vary between 2.5 to 15 ps across PVT, set initial delay
# to 0 and let the software configure it.
p_DELAY_FORMAT="COUNT", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0, p_DELAY_FORMAT="COUNT", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(), i_CLK=ClockSignal(),