test/test_init: fix
This commit is contained in:
Florent Kermarrec
parent
5b48eb278a
commit
40b4c62889
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@ -1,100 +1,23 @@
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#ifndef __GENERATED_SDRAM_PHY_H
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#define __GENERATED_SDRAM_PHY_H
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#include <hw/common.h>
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#include <generated/csr.h>
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#include <hw/flags.h>
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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#define DFII_NPHASES 4
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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static void cdelay(int i);
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ddrx_mr1 = 0x6
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__attribute__((unused)) static void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p1(int cmd)
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{
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sdram_dfii_pi1_command_write(cmd);
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sdram_dfii_pi1_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p2(int cmd)
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{
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sdram_dfii_pi2_command_write(cmd);
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sdram_dfii_pi2_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p3(int cmd)
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{
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sdram_dfii_pi3_command_write(cmd);
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sdram_dfii_pi3_command_issue_write(1);
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}
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
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#define command_prd(X) command_p1(X)
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#define command_pwr(X) command_p2(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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const unsigned long sdram_dfii_pix_wrdata_addr[4] = {
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI3_WRDATA_ADDR
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};
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const unsigned long sdram_dfii_pix_rddata_addr[4] = {
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI3_RDDATA_ADDR
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};
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#define DDRX_MR1 6
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static void init_sequence(void)
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{
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/* Release reset */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(50000);
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(10000);
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/* Load Mode Register 2, CWL=6 */
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sdram_dfii_pi0_address_write(0x208);
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sdram_dfii_pi0_baddress_write(2);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 3 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(3);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 1 */
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sdram_dfii_pi0_address_write(0x6);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 0, CL=7, BL=8 */
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sdram_dfii_pi0_address_write(0x930);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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/* ZQ Calibration */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif
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init_sequence = [
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("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
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("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
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("Load Mode Register 2, CWL=6", 520, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 1", 6, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 0, CL=7, BL=8", 2352, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
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]
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@ -1,115 +1,26 @@
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#ifndef __GENERATED_SDRAM_PHY_H
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#define __GENERATED_SDRAM_PHY_H
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#include <hw/common.h>
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#include <generated/csr.h>
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#include <hw/flags.h>
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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#define DFII_NPHASES 4
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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static void cdelay(int i);
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ddrx_mr1 = 0x301
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__attribute__((unused)) static void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p1(int cmd)
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{
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sdram_dfii_pi1_command_write(cmd);
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sdram_dfii_pi1_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p2(int cmd)
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{
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sdram_dfii_pi2_command_write(cmd);
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sdram_dfii_pi2_command_issue_write(1);
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}
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__attribute__((unused)) static void command_p3(int cmd)
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{
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sdram_dfii_pi3_command_write(cmd);
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sdram_dfii_pi3_command_issue_write(1);
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}
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi3_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi3_baddress_write(X)
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#define command_prd(X) command_p1(X)
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#define command_pwr(X) command_p3(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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const unsigned long sdram_dfii_pix_wrdata_addr[4] = {
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI3_WRDATA_ADDR
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};
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const unsigned long sdram_dfii_pix_rddata_addr[4] = {
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI3_RDDATA_ADDR
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};
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#define DDRX_MR1 769
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static void init_sequence(void)
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{
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/* Release reset */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(50000);
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(10000);
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/* Load Mode Register 3 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(3);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 6 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(6);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 5 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(5);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 4 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(4);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 2, CWL=9 */
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sdram_dfii_pi0_address_write(0x200);
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sdram_dfii_pi0_baddress_write(2);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 1 */
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sdram_dfii_pi0_address_write(0x301);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 0, CL=11, BL=8 */
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sdram_dfii_pi0_address_write(0x110);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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/* ZQ Calibration */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif
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init_sequence = [
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("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
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("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
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("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 6", 0, 6, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 5", 0, 5, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 0, CL=11, BL=8", 272, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
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]
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@ -1,78 +1,21 @@
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#ifndef __GENERATED_SDRAM_PHY_H
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#define __GENERATED_SDRAM_PHY_H
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#include <hw/common.h>
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#include <generated/csr.h>
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#include <hw/flags.h>
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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#define DFII_NPHASES 1
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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static void cdelay(int i);
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__attribute__((unused)) static void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
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#define command_prd(X) command_p0(X)
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#define command_pwr(X) command_p0(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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const unsigned long sdram_dfii_pix_wrdata_addr[1] = {
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR
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};
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const unsigned long sdram_dfii_pix_rddata_addr[1] = {
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR
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};
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static void init_sequence(void)
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{
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(20000);
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/* Precharge All */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register / Reset DLL, CL=2, BL=1 */
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sdram_dfii_pi0_address_write(0x120);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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/* Precharge All */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Auto Refresh */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
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cdelay(4);
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/* Auto Refresh */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
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cdelay(4);
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/* Load Mode Register / CL=2, BL=1 */
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sdram_dfii_pi0_address_write(0x20);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif
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init_sequence = [
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("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 20000),
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("Precharge All", 1024, 0, dfii_command_ras|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register / Reset DLL, CL=2, BL=1", 288, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("Precharge All", 1024, 0, dfii_command_ras|dfii_command_we|dfii_command_cs, 0),
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("Auto Refresh", 0, 0, dfii_command_ras|dfii_command_cas|dfii_command_cs, 4),
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("Auto Refresh", 0, 0, dfii_command_ras|dfii_command_cas|dfii_command_cs, 4),
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("Load Mode Register / CL=2, BL=1", 32, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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]
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@ -24,7 +24,7 @@ class TestInit(unittest.TestCase):
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True)
|
||||
self.assertEqual(compare_with_reference(c_header, "sdr_init.py"), True)
|
||||
self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
|
||||
|
||||
def test_ddr3(self):
|
||||
from litex.boards.targets.kc705 import BaseSoC
|
||||
|
|
@ -32,7 +32,7 @@ class TestInit(unittest.TestCase):
|
|||
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True)
|
||||
self.assertEqual(compare_with_reference(c_header, "ddr3_init.py"), True)
|
||||
self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True)
|
||||
|
||||
def test_ddr4(self):
|
||||
from litex.boards.targets.kcu105 import BaseSoC
|
||||
|
|
@ -40,4 +40,4 @@ class TestInit(unittest.TestCase):
|
|||
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
|
||||
self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
|
||||
self.assertEqual(compare_with_reference(c_header, "ddr4_init.py"), True)
|
||||
self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)
|
||||
|
|
|
|||
Loading…
Reference in New Issue