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test/test_init: fix

This commit is contained in:
Florent Kermarrec 2019-09-09 15:17:43 +02:00
parent 5b48eb278a
commit 40b4c62889
5 changed files with 65 additions and 288 deletions
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0
test/reference/__init__.py
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117
test/reference/ddr3_init.py
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@ -1,100 +1,23 @@
#ifndef __GENERATED_SDRAM_PHY_H dfii_control_sel = 0x01
#define __GENERATED_SDRAM_PHY_H dfii_control_cke = 0x02
#include <hw/common.h> dfii_control_odt = 0x04
#include <generated/csr.h> dfii_control_reset_n = 0x08
#include <hw/flags.h>
#define DFII_NPHASES 4 dfii_command_cs = 0x01
dfii_command_we = 0x02
dfii_command_cas = 0x04
dfii_command_ras = 0x08
dfii_command_wrdata = 0x10
dfii_command_rddata = 0x20
static void cdelay(int i); ddrx_mr1 = 0x6
__attribute__((unused)) static void command_p0(int cmd) init_sequence = [
{ ("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
sdram_dfii_pi0_command_write(cmd); ("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
sdram_dfii_pi0_command_issue_write(1); ("Load Mode Register 2, CWL=6", 520, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
} ("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
__attribute__((unused)) static void command_p1(int cmd) ("Load Mode Register 1", 6, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
{ ("Load Mode Register 0, CL=7, BL=8", 2352, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
sdram_dfii_pi1_command_write(cmd); ("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
sdram_dfii_pi1_command_issue_write(1); ]
}
__attribute__((unused)) static void command_p2(int cmd)
{
sdram_dfii_pi2_command_write(cmd);
sdram_dfii_pi2_command_issue_write(1);
}
__attribute__((unused)) static void command_p3(int cmd)
{
sdram_dfii_pi3_command_write(cmd);
sdram_dfii_pi3_command_issue_write(1);
}
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
#define command_prd(X) command_p1(X)
#define command_pwr(X) command_p2(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[4] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
CSR_SDRAM_DFII_PI3_WRDATA_ADDR
};
const unsigned long sdram_dfii_pix_rddata_addr[4] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
CSR_SDRAM_DFII_PI3_RDDATA_ADDR
};
#define DDRX_MR1 6
static void init_sequence(void)
{
/* Release reset */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(50000);
/* Bring CKE high */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(10000);
/* Load Mode Register 2, CWL=6 */
sdram_dfii_pi0_address_write(0x208);
sdram_dfii_pi0_baddress_write(2);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 3 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(3);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 1 */
sdram_dfii_pi0_address_write(0x6);
sdram_dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 0, CL=7, BL=8 */
sdram_dfii_pi0_address_write(0x930);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* ZQ Calibration */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
#endif

135
test/reference/ddr4_init.py
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@ -1,115 +1,26 @@
#ifndef __GENERATED_SDRAM_PHY_H dfii_control_sel = 0x01
#define __GENERATED_SDRAM_PHY_H dfii_control_cke = 0x02
#include <hw/common.h> dfii_control_odt = 0x04
#include <generated/csr.h> dfii_control_reset_n = 0x08
#include <hw/flags.h>
#define DFII_NPHASES 4 dfii_command_cs = 0x01
dfii_command_we = 0x02
dfii_command_cas = 0x04
dfii_command_ras = 0x08
dfii_command_wrdata = 0x10
dfii_command_rddata = 0x20
static void cdelay(int i); ddrx_mr1 = 0x301
__attribute__((unused)) static void command_p0(int cmd) init_sequence = [
{ ("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
sdram_dfii_pi0_command_write(cmd); ("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
sdram_dfii_pi0_command_issue_write(1); ("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
} ("Load Mode Register 6", 0, 6, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
__attribute__((unused)) static void command_p1(int cmd) ("Load Mode Register 5", 0, 5, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
{ ("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
sdram_dfii_pi1_command_write(cmd); ("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
sdram_dfii_pi1_command_issue_write(1); ("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
} ("Load Mode Register 0, CL=11, BL=8", 272, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
__attribute__((unused)) static void command_p2(int cmd) ("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
{ ]
sdram_dfii_pi2_command_write(cmd);
sdram_dfii_pi2_command_issue_write(1);
}
__attribute__((unused)) static void command_p3(int cmd)
{
sdram_dfii_pi3_command_write(cmd);
sdram_dfii_pi3_command_issue_write(1);
}
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi3_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi3_baddress_write(X)
#define command_prd(X) command_p1(X)
#define command_pwr(X) command_p3(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[4] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
CSR_SDRAM_DFII_PI3_WRDATA_ADDR
};
const unsigned long sdram_dfii_pix_rddata_addr[4] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
CSR_SDRAM_DFII_PI3_RDDATA_ADDR
};
#define DDRX_MR1 769
static void init_sequence(void)
{
/* Release reset */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(50000);
/* Bring CKE high */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(10000);
/* Load Mode Register 3 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(3);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 6 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(6);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 5 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(5);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 4 */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(4);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 2, CWL=9 */
sdram_dfii_pi0_address_write(0x200);
sdram_dfii_pi0_baddress_write(2);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 1 */
sdram_dfii_pi0_address_write(0x301);
sdram_dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 0, CL=11, BL=8 */
sdram_dfii_pi0_address_write(0x110);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* ZQ Calibration */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
#endif

95
test/reference/sdr_init.py
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@ -1,78 +1,21 @@
#ifndef __GENERATED_SDRAM_PHY_H dfii_control_sel = 0x01
#define __GENERATED_SDRAM_PHY_H dfii_control_cke = 0x02
#include <hw/common.h> dfii_control_odt = 0x04
#include <generated/csr.h> dfii_control_reset_n = 0x08
#include <hw/flags.h>
#define DFII_NPHASES 1 dfii_command_cs = 0x01
dfii_command_we = 0x02
dfii_command_cas = 0x04
dfii_command_ras = 0x08
dfii_command_wrdata = 0x10
dfii_command_rddata = 0x20
static void cdelay(int i); init_sequence = [
("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 20000),
__attribute__((unused)) static void command_p0(int cmd) ("Precharge All", 1024, 0, dfii_command_ras|dfii_command_we|dfii_command_cs, 0),
{ ("Load Mode Register / Reset DLL, CL=2, BL=1", 288, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
sdram_dfii_pi0_command_write(cmd); ("Precharge All", 1024, 0, dfii_command_ras|dfii_command_we|dfii_command_cs, 0),
sdram_dfii_pi0_command_issue_write(1); ("Auto Refresh", 0, 0, dfii_command_ras|dfii_command_cas|dfii_command_cs, 4),
} ("Auto Refresh", 0, 0, dfii_command_ras|dfii_command_cas|dfii_command_cs, 4),
("Load Mode Register / CL=2, BL=1", 32, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
]
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
#define command_prd(X) command_p0(X)
#define command_pwr(X) command_p0(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[1] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR
};
const unsigned long sdram_dfii_pix_rddata_addr[1] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR
};
static void init_sequence(void)
{
/* Bring CKE high */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(20000);
/* Precharge All */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register / Reset DLL, CL=2, BL=1 */
sdram_dfii_pi0_address_write(0x120);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* Precharge All */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Auto Refresh */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
/* Auto Refresh */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
/* Load Mode Register / CL=2, BL=1 */
sdram_dfii_pi0_address_write(0x20);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
#endif

6
test/test_init.py
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@ -24,7 +24,7 @@ class TestInit(unittest.TestCase):
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True) self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True)
self.assertEqual(compare_with_reference(c_header, "sdr_init.py"), True) self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
def test_ddr3(self): def test_ddr3(self):
from litex.boards.targets.kc705 import BaseSoC from litex.boards.targets.kc705 import BaseSoC
@ -32,7 +32,7 @@ class TestInit(unittest.TestCase):
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True) self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True)
self.assertEqual(compare_with_reference(c_header, "ddr3_init.py"), True) self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True)
def test_ddr4(self): def test_ddr4(self):
from litex.boards.targets.kcu105 import BaseSoC from litex.boards.targets.kcu105 import BaseSoC
@ -40,4 +40,4 @@ class TestInit(unittest.TestCase):
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True) self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
self.assertEqual(compare_with_reference(c_header, "ddr4_init.py"), True) self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)