litedram_gen: review #234: rename --module-name to --name add also adapt init file renaming.
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@ -682,7 +682,7 @@ def main():
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parser.set_defaults(output_dir="build")
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parser.set_defaults(output_dir="build")
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parser.add_argument("config", help="YAML config file")
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parser.add_argument("config", help="YAML config file")
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parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation")
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parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation")
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parser.add_argument("--module-name", default="litedram_core", help="Set Verilog module name")
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parser.add_argument("--name", default="litedram_core", help="Standalone core/module name")
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args = parser.parse_args()
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args = parser.parse_args()
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core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
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core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
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@ -716,15 +716,15 @@ def main():
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
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builder = Builder(soc, **builder_arguments)
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builder = Builder(soc, **builder_arguments)
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builder.build(build_name=args.module_name, regular_comb=False)
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builder.build(build_name=args.name, regular_comb=False)
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if soc.cpu_type is not None:
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if soc.cpu_type is not None:
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init_filename = "mem.init"
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init_filename = "mem.init"
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os.system("mv {} {}".format(
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os.system("mv {} {}".format(
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os.path.join(builder.gateware_dir, init_filename),
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os.path.join(builder.gateware_dir, init_filename),
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os.path.join(builder.gateware_dir, "litedram_core.init"),
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os.path.join(builder.gateware_dir, f"{args.name}.init"),
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))
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))
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replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"), init_filename, "litedram_core.init")
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replace_in_file(os.path.join(builder.gateware_dir, f"{args.name}.v"), init_filename, f"{args.name}.init")
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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main()
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