Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litedram_gen: review #234: rename --module-name to --name add also adapt init file renaming.

This commit is contained in:
Florent Kermarrec 2021-03-01 09:25:16 +01:00
parent aa3ed0bbff
commit 424b5f956a
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litedram/gen.py
View File

@ -682,7 +682,7 @@ def main():
parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file")
parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation")
parser.add_argument("--module-name", default="litedram_core", help="Set Verilog module name")
parser.add_argument("--name", default="litedram_core", help="Standalone core/module name")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
@ -716,15 +716,15 @@ def main():
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
builder = Builder(soc, **builder_arguments)
builder.build(build_name=args.module_name, regular_comb=False)
builder.build(build_name=args.name, regular_comb=False)
if soc.cpu_type is not None:
init_filename = "mem.init"
os.system("mv {} {}".format(
os.path.join(builder.gateware_dir, init_filename),
os.path.join(builder.gateware_dir, "litedram_core.init"),
os.path.join(builder.gateware_dir, f"{args.name}.init"),
))
replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"), init_filename, "litedram_core.init")
replace_in_file(os.path.join(builder.gateware_dir, f"{args.name}.v"), init_filename, f"{args.name}.init")
if __name__ == "__main__":
main()