modules: extend parsing of timings to always allow (ck, ns) format
This commit is contained in:
Jędrzej Boczar
parent
5a114be7e5
commit
436bfc4fbd
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@ -294,6 +294,12 @@ def parse_spd_hexdump(filename):
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# SDRAMModule --------------------------------------------------------------------------------------
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Frac = namedtuple("Frac", ["num", "denom"])
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class Timing(namedtuple("Timing", ["ck", "ns"])):
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def __add__(self, other):
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return Timing(self.ck + other.ck, self.ns + other.ns)
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class SDRAMModule:
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"""SDRAM module geometry and timings.
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@ -320,68 +326,82 @@ class SDRAMModule:
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if (fine_refresh_mode is None) and (self.memtype == "DDR4"):
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fine_refresh_mode = "1x"
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self.timing_settings = TimingSettings(
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tRP = self.ns_to_cycles(self.get("tRP")),
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tRCD = self.ns_to_cycles(self.get("tRCD")),
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tWR = self.ns_to_cycles(self.get("tWR")),
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tREFI = self.ns_to_cycles(self.get("tREFI", fine_refresh_mode), False),
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tRFC = self.ck_ns_to_cycles(*self.get("tRFC", fine_refresh_mode)),
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tWTR = self.ck_ns_to_cycles(*self.get("tWTR")),
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tFAW = None if self.get("tFAW") is None else self.ck_ns_to_cycles(*self.get("tFAW")),
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tCCD = None if self.get("tCCD") is None else self.ck_ns_to_cycles(*self.get("tCCD")),
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tRRD = None if self.get("tRRD") is None else self.ck_ns_to_cycles(*self.get("tRRD")),
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tRC = None if self.get("tRAS") is None else self.ns_to_cycles(self.get("tRP") + self.get("tRAS")),
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tRAS = None if self.get("tRAS") is None else self.ns_to_cycles(self.get("tRAS")),
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tZQCS = None if self.get("tZQCS") is None else self.ck_ns_to_cycles(*self.get("tZQCS"))
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tRP = self.ck_ns_to_cycles(self.get("tRP")),
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tRCD = self.ck_ns_to_cycles(self.get("tRCD")),
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tWR = self.ck_ns_to_cycles(self.get("tWR")),
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tREFI = self.ck_ns_to_cycles(self.get("tREFI", fine_refresh_mode), margin=False),
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tRFC = self.ck_ns_to_cycles(self.get("tRFC", fine_refresh_mode)),
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tWTR = self.ck_ns_to_cycles(self.get("tWTR")),
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tFAW = None if self.get("tFAW") is None else self.ck_ns_to_cycles(self.get("tFAW")),
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tCCD = None if self.get("tCCD") is None else self.ck_ns_to_cycles(self.get("tCCD")),
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tRRD = None if self.get("tRRD") is None else self.ck_ns_to_cycles(self.get("tRRD")),
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tRC = None if self.get("tRAS") is None else self.ck_ns_to_cycles(self.get("tRP") + self.get("tRAS")),
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tRAS = None if self.get("tRAS") is None else self.ck_ns_to_cycles(self.get("tRAS")),
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tZQCS = None if self.get("tZQCS") is None else self.ck_ns_to_cycles(self.get("tZQCS"))
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)
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self.timing_settings.fine_refresh_mode = fine_refresh_mode
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def get(self, name, key=None):
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r = None
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if name in _speedgrade_timings:
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if hasattr(self, "speedgrade_timings"):
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speedgrade = "default" if self.speedgrade is None else self.speedgrade
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r = getattr(self.speedgrade_timings[speedgrade], name)
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else:
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name = name + "_" + self.speedgrade if self.speedgrade is not None else name
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try:
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r = getattr(self, name)
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except:
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pass
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assert name in _speedgrade_timings + _technology_timings, "Unknown name: {}".format(name)
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timing = self.get_timing(name)
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if timing is None:
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return None
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if (timing is not None) and (key is not None):
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timing = timing[key]
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if isinstance(timing, tuple):
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ck, ns = timing
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else:
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if hasattr(self, "technology_timings"):
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r = getattr(self.technology_timings, name)
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else:
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try:
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r = getattr(self, name)
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except:
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pass
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if (r is not None) and (key is not None):
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r = r[key]
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return r
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ck, ns = 0, timing
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ck = ck or 0
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ns = ns or 0
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return Timing(ck, ns)
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def get_timing(self, name):
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if name in _speedgrade_timings:
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return self.get_speedgrade_timing(name)
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return self.get_technology_timing(name)
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def get_speedgrade_timing(self, name):
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if hasattr(self, "speedgrade_timings"):
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speedgrade = "default" if self.speedgrade is None else self.speedgrade
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return getattr(self.speedgrade_timings[speedgrade], name)
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name = name + "_" + self.speedgrade if self.speedgrade is not None else name
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try:
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return getattr(self, name)
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except:
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pass
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def get_technology_timing(self, name):
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if hasattr(self, "technology_timings"):
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return getattr(self.technology_timings, name)
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else:
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try:
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return getattr(self, name)
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except:
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pass
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def ns_to_cycles(self, t, margin=True):
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clk_period_ns = 1e9/self.clk_freq
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if margin:
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margins = {
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"1:1" : 0,
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"1:2" : clk_period_ns/2,
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"1:4" : 3*clk_period_ns/4
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}
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t += margins[self.rate]
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t += self.margin if margin else 0
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return ceil(t/clk_period_ns)
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def ck_to_cycles(self, c):
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d = {
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"1:1" : 1,
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"1:2" : 2,
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"1:4" : 4
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}
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return ceil(c/d[self.rate])
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return ceil(c/self.rate_frac.denom)
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def ck_ns_to_cycles(self, c, t):
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c = 0 if c is None else c
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t = 0 if t is None else t
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return max(self.ck_to_cycles(c), self.ns_to_cycles(t))
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def ck_ns_to_cycles(self, timing, **kwargs):
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return max(self.ck_to_cycles(timing.ck), self.ns_to_cycles(timing.ns, **kwargs))
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@property
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def rate_frac(self):
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num, denom = map(int, self.rate.split(":"))
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assert num == 1, "Rate: numerator must be 1: {}".format(self.rate)
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return Frac(num, denom)
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@property
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def margin(self):
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clk_period_ns = 1e9 / self.clk_freq
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frac = self.rate_frac
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return clk_period_ns * (1 - frac.num/frac.denom)
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@classmethod
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def from_spd_data(cls, spd_data, clk_freq, fine_refresh_mode=None):
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