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litedram_gen: Fix UART interrupt/polling.

This commit is contained in:
Florent Kermarrec 2021-09-16 17:41:40 +02:00
parent e0e204a514
commit 43856dadd6
1 changed files with 4 additions and 1 deletions
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5
litedram/gen.py
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@ -514,7 +514,10 @@ class LiteDRAMCore(SoCCore):
else: else:
self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200) self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200)
self.submodules.uart = UART(self.uart_phy) self.submodules.uart = UART(self.uart_phy)
self.add_interrupt("uart") if self.irq.enabled:
self.irq.add("uart", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
if isinstance(platform, SimPlatform): if isinstance(platform, SimPlatform):