litedram_gen: Fix UART interrupt/polling.

2021-09-16 17:41:40 +02:00 · 2021-09-16 17:41:40 +02:00 · 43856dadd6
parent e0e204a514
commit 43856dadd6
1 changed files with 4 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -514,7 +514,10 @@ class LiteDRAMCore(SoCCore):
        else:
            self.submodules.uart_phy = RS232PHY(platform.request("uart"), self.clk_freq, 115200)
            self.submodules.uart = UART(self.uart_phy)
-        self.add_interrupt("uart")
+        if self.irq.enabled:
+            self.irq.add("uart", use_loc_if_exists=True)
+        else:
+            self.add_constant("UART_POLLING")

        # CRG --------------------------------------------------------------------------------------
        if isinstance(platform, SimPlatform):