test/test_axi: change order of the tests
This commit is contained in:
Florent Kermarrec
parent
070cc26994
commit
4470f32ef8
166
test/test_axi.py
166
test/test_axi.py
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@ -12,6 +12,89 @@ from litex.gen.sim import *
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Burst:
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def __init__(self, type, addr, len, size):
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self.type = type
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self.addr = addr
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == burst_types["wrap"]:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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return r
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# dut
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(burst_types["fixed"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["incr"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["wrap"], 4, 4-1, log2_int(2)))
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# generate expexted dut output (beats for reference)
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators, vcd_name="burst2beat.vcd")
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self.assertEqual(self.errors, 0)
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def test_axi2native(self):
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class Access:
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def __init__(self, addr, data, id):
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@ -128,86 +211,3 @@ class TestAXI(unittest.TestCase):
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self.assertEqual(self.reads_data_errors, 0)
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self.assertEqual(self.reads_id_errors, 0)
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self.assertEqual(self.reads_last_errors, 0)
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def test_burst2beat(self):
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Burst:
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def __init__(self, type, addr, len, size):
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self.type = type
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self.addr = addr
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == burst_types["wrap"]:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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return r
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# dut
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(burst_types["fixed"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["incr"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["wrap"], 4, 4-1, log2_int(2)))
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# generate expexted dut output (beats for reference)
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators, vcd_name="burst2beat.vcd")
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self.assertEqual(self.errors, 0)
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