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litedram
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gen/init: Simplify Electrical Settings collection (and make them optional with litedram_gen). 

When not specified in litedram_gen, the default settings will be used.
This commit is contained in:
Florent Kermarrec 2021-10-07 13:44:25 +02:00
parent e1512553f8
commit 460dcc0a9e
3 changed files with 34 additions and 50 deletions
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11
litedram/common.py
View File

@ -236,9 +236,16 @@ class PhySettings(Settings):
# rtt_wr: Writes on-die termination impedance
# ron: Output driver impedance
# tdqs: Termination Data Strobe enable.
def add_electrical_settings(self, rtt_nom, rtt_wr, ron, tdqs=False):
def add_electrical_settings(self, rtt_nom=None, rtt_wr=None, ron=None, tdqs=None):
assert self.memtype in ["DDR3", "DDR4"]
self.set_attributes(locals())
if rtt_nom is not None:
self.rtt = rtt_nom
if rtt_wr is not None:
self.rtt_wr = rtt_wr
if ron is not None:
self.ron = ron
if tdqs is not None:
self.tdqs = tdqs
# Optional RDIMM configuration
def set_rdimm(self, tck, rcd_pll_bypass, rcd_ca_cs_drive, rcd_odt_cke_drive, rcd_clk_drive):

31
litedram/gen.py
View File

@ -542,6 +542,12 @@ class LiteDRAMCore(SoCCore):
"DDR3": "1:4",
"DDR4": "1:4"}[core_config["memtype"]])
# Collect Electrical Settings.
electrical_settings_kwargs = {}
for name in ["rtt_nom", "rtt_wr", "ron"]:
if core_config.get(name, None) is not None:
electrical_settings_kwargs[name] = core_config[name]
# Sim.
if isinstance(platform, SimPlatform):
from litex.tools.litex_sim import get_sdram_phy_settings
@ -568,11 +574,8 @@ class LiteDRAMCore(SoCCore):
self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq,
cmd_delay = core_config["cmd_delay"])
self.ddrphy.settings.add_electrical_settings(
rtt_nom = core_config["rtt_nom"],
rtt_wr = core_config["rtt_wr"],
ron = core_config["ron"])
cmd_delay = core_config.get("cmd_delay", 0))
self.ddrphy.settings.add_electrical_settings(**electrical_settings_kwargs)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
self.comb += crg.reset.eq(self.ddrphy.init.reset)
@ -587,10 +590,7 @@ class LiteDRAMCore(SoCCore):
iodelay_clk_freq = core_config["iodelay_clk_freq"],
cmd_latency = core_config["cmd_latency"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom = core_config["rtt_nom"],
rtt_wr = core_config["rtt_wr"],
ron = core_config["ron"])
self.ddrphy.settings.add_electrical_settings(**electrical_settings_kwargs)
# USDDRPHY.
elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]:
@ -600,19 +600,16 @@ class LiteDRAMCore(SoCCore):
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = core_config["iodelay_clk_freq"],
cmd_latency = core_config["cmd_latency"])
self.ddrphy.settings.add_electrical_settings(
rtt_nom = core_config["rtt_nom"],
rtt_wr = core_config["rtt_wr"],
ron = core_config["ron"])
self.ddrphy.settings.add_electrical_settings(**electrical_settings_kwargs)
else:
raise NotImplementedError
# Controller Settings.
controller_kwargs = {}
# Collect Controller Settings.
controller_settings_kwargs = {}
for name in inspect.getfullargspec(ControllerSettings. __init__).args:
if core_config.get(name, None) is not None:
controller_kwargs[name] = core_config[name]
controller_settings = controller_settings = ControllerSettings(**controller_kwargs)
controller_settings_kwargs[name] = core_config[name]
controller_settings = controller_settings = ControllerSettings(**controller_settings_kwargs)
# Add LiteDRAM Core to SoC.
self.add_sdram("sdram",

40
litedram/init.py
View File

@ -192,21 +192,11 @@ def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
"34ohm" : 1,
}
# default electrical settings (point to point)
rtt_nom = "60ohm"
rtt_wr = "60ohm"
ron = "34ohm"
tdqs = 0
# override electrical settings if specified
if hasattr(phy_settings, "rtt_nom"):
rtt_nom = phy_settings.rtt_nom
if hasattr(phy_settings, "rtt_wr"):
rtt_wr = phy_settings.rtt_wr
if hasattr(phy_settings, "ron"):
ron = phy_settings.ron
if getattr(phy_settings, "tdqs", False):
tdqs = 1
# Get Electrical Settings (or use default: Point to Point).
rtt_nom = getattr(phy_settings, "rtt_nom", "60ohm")
rtt_wr = getattr(phy_settings, "rtt_wr", "60ohm")
ron = getattr(phy_settings, "ron", "34ohm")
tdqs = getattr(phy_settings, "tdqs", 0)
wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
mr0 = format_mr0(bl, cl, wr, 1)
@ -354,24 +344,14 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
"48ohm" : 0b01,
}
# default electrical settings (point to point)
rtt_nom = "40ohm"
rtt_wr = "120ohm"
ron = "34ohm"
tdqs = 0
# Get Electrical Settings (or use default: Point to Point).
rtt_nom = getattr(phy_settings, "rtt_nom", "40ohm")
rtt_wr = getattr(phy_settings, "rtt_wr", "120ohm")
ron = getattr(phy_settings, "ron", "34ohm")
tdqs = getattr(phy_settings, "tdqs", 0)
dm = 1
assert not (dm and tdqs)
# override electrical settings if specified
if hasattr(phy_settings, "rtt_nom"):
rtt_nom = phy_settings.rtt_nom
if hasattr(phy_settings, "rtt_wr"):
rtt_wr = phy_settings.rtt_wr
if hasattr(phy_settings, "ron"):
ron = phy_settings.ron
if getattr(phy_settings, "tdqs", False):
tdqs = 1
wr = max(timing_settings.tWTR*phy_settings.nphases, 10) # >= ceiling(tWR/tCK)
mr0 = format_mr0(bl, cl, wr, 1)
mr1 = format_mr1(1, z_to_ron[ron], z_to_rtt_nom[rtt_nom], tdqs)