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move crossbar to frontend, adapt core

This commit is contained in:
Florent Kermarrec 2016-04-29 16:48:35 +02:00
parent 41c76899d5
commit 47f2859091
8 changed files with 52 additions and 47 deletions
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35
litedram/bus.py Normal file
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@ -0,0 +1,35 @@
from functools import reduce
from operator import or_
from litex.gen import *
from litex.gen.genlib.record import *
class Interface(Record):
def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
self.aw = aw
self.dw = dw
self.nbanks = nbanks
self.req_queue_size = req_queue_size
self.read_latency = read_latency
self.write_latency = write_latency
bank_layout = [
("adr", aw, DIR_M_TO_S),
("we", 1, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("req_ack", 1, DIR_S_TO_M),
("dat_w_ack", 1, DIR_S_TO_M),
("dat_r_ack", 1, DIR_S_TO_M),
("lock", 1, DIR_S_TO_M)
]
if nbanks > 1:
layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
else:
layout = bank_layout
layout += [
("dat_w", dw, DIR_M_TO_S),
("dat_we", dw//8, DIR_M_TO_S),
("dat_r", dw, DIR_S_TO_M)
]
Record.__init__(self, layout)

2
litedram/core/__init__.py
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@ -1 +1 @@
from litedram.lasmicon.core import ControllerSettings, LASMIcon
from litedram.core.controller import ControllerSettings, LiteDRAMController

4
litedram/core/bankmachine.py
View File

@ -3,7 +3,7 @@ from litex.gen.genlib.roundrobin import *
from litex.gen.genlib.fsm import FSM, NextState
from litex.gen.genlib.fifo import SyncFIFO
from litedram.lasmicon.multiplexer import *
from litedram.core.multiplexer import *
class _AddressSlicer:
@ -32,7 +32,7 @@ class BankMachine(Module):
self.refresh_gnt = Signal()
self.cmd = CommandRequestRW(geom_settings.addressbits, geom_settings.bankbits)
###
# # #
# Request FIFO
layout = [("we", 1), ("adr", len(req.adr))]

14
litedram/core/core.py → litedram/core/controller.py
View File

@ -1,10 +1,10 @@
from litex.gen import *
from litedram.phy import dfi
from litedram import lasmi_bus
from litedram.lasmicon.refresher import *
from litedram.lasmicon.bankmachine import *
from litedram.lasmicon.multiplexer import *
from litedram import bus
from litedram.core.refresher import *
from litedram.core.bankmachine import *
from litedram.core.multiplexer import *
class ControllerSettings:
@ -15,7 +15,7 @@ class ControllerSettings:
self.with_bandwidth = with_bandwidth
class LASMIcon(Module):
class LiteDRAMController(Module):
def __init__(self, phy_settings, geom_settings, timing_settings,
controller_settings=None):
if controller_settings is None:
@ -30,7 +30,7 @@ class LASMIcon(Module):
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.lasmic = lasmi_bus.Interface(
self.lasmic = bus.Interface(
aw=geom_settings.rowbits + geom_settings.colbits - address_align,
dw=phy_settings.dfi_databits*phy_settings.nphases,
nbanks=2**geom_settings.bankbits,
@ -39,7 +39,7 @@ class LASMIcon(Module):
write_latency=phy_settings.write_latency+1)
self.nrowbits = geom_settings.colbits - address_align
###
# # #
self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)

4
litedram/core/multiplexer.py
View File

@ -5,7 +5,7 @@ from litex.gen import *
from litex.gen.genlib.roundrobin import *
from litex.gen.genlib.fsm import FSM, NextState
from litedram.lasmicon.perf import Bandwidth
from litedram.core.perf import Bandwidth
from litex.soc.interconnect.csr import AutoCSR
@ -36,7 +36,7 @@ class _CommandChooser(Module):
# NB: cas_n/ras_n/we_n are 1 when stb is inactive
self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba))
###
# # #
rr = RoundRobin(len(requests), SP_CE)
self.submodules += rr

2
litedram/core/perf.py
View File

@ -10,7 +10,7 @@ class Bandwidth(Module, AutoCSR):
self._nwrites = CSRStatus(period_bits)
self._data_width = CSRStatus(bits_for(data_width), reset=data_width)
###
# # #
cmd_stb = Signal()
cmd_ack = Signal()

4
litedram/core/refresher.py
View File

@ -2,7 +2,7 @@ from litex.gen import *
from litex.gen.genlib.misc import timeline
from litex.gen.genlib.fsm import FSM
from litedram.lasmicon.multiplexer import *
from litedram.core.multiplexer import *
class Refresher(Module):
@ -11,7 +11,7 @@ class Refresher(Module):
self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.cmd = CommandRequest(a, ba)
###
# # #
# Refresh sequence generator:
# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done

34
litedram/lasmi_bus.py → litedram/frontend/crossbar.py
View File

@ -3,38 +3,8 @@ from operator import or_
from litex.gen import *
from litex.gen.genlib import roundrobin
from litex.gen.genlib.record import *
class Interface(Record):
def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
self.aw = aw
self.dw = dw
self.nbanks = nbanks
self.req_queue_size = req_queue_size
self.read_latency = read_latency
self.write_latency = write_latency
bank_layout = [
("adr", aw, DIR_M_TO_S),
("we", 1, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("req_ack", 1, DIR_S_TO_M),
("dat_w_ack", 1, DIR_S_TO_M),
("dat_r_ack", 1, DIR_S_TO_M),
("lock", 1, DIR_S_TO_M)
]
if nbanks > 1:
layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
else:
layout = bank_layout
layout += [
("dat_w", dw, DIR_M_TO_S),
("dat_we", dw//8, DIR_M_TO_S),
("dat_r", dw, DIR_S_TO_M)
]
Record.__init__(self, layout)
from litedram.bus import *
def _getattr_all(l, attr):
it = iter(l)
@ -45,7 +15,7 @@ def _getattr_all(l, attr):
return r
class LASMIxbar(Module):
class LiteDRAMCrossbar(Module):
def __init__(self, controllers, cba_shift):
self._controllers = controllers
self._cba_shift = cba_shift