frontend/wishbone: simplify/review and get FSM back (ease comprehension).
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@ -36,37 +36,44 @@ class LiteDRAMWishbone2Native(Module):
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adr_offset = base_address >> log2_int(port.data_width//8)
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adr_offset = base_address >> log2_int(port.data_width//8)
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# latch ready signals of cmd/wdata and then wait until all are ready
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# Write Datapath ---------------------------------------------------------------------------
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cmd_consumed = Signal()
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wdata_consumed = Signal()
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self.sync += [
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If(wishbone.ack,
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cmd_consumed.eq(0),
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wdata_consumed.eq(0),
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).Else(
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If(port.cmd.valid & port.cmd.ready, cmd_consumed.eq(1)),
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If(port.wdata.valid & port.wdata.ready, wdata_consumed.eq(1)),
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),
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]
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ack_cmd = Signal()
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ack_wdata = Signal()
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ack_rdata = Signal()
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self.comb += [
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self.comb += [
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port.cmd.addr.eq(wishbone.adr - adr_offset),
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port.cmd.we.eq(wishbone.we),
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port.wdata.data.eq(wishbone.dat_w),
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port.wdata.data.eq(wishbone.dat_w),
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port.wdata.we.eq(wishbone.sel),
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port.wdata.we.eq(wishbone.sel),
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wishbone.dat_r.eq(port.rdata.data),
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# always wait for reads, flush write when transaction ends
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port.flush.eq(~wishbone.cyc),
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port.cmd.last.eq(~wishbone.we),
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# make sure cmd/wdata won't stay valid after it is consumed
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port.cmd.valid.eq(wishbone.cyc & wishbone.stb & ~cmd_consumed),
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port.wdata.valid.eq((port.cmd.valid | cmd_consumed) & port.cmd.we & ~wdata_consumed),
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port.rdata.ready.eq((port.cmd.valid | cmd_consumed) & ~port.cmd.we),
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wishbone.ack.eq(ack_cmd & ((wishbone.we & ack_wdata) | (~wishbone.we & ack_rdata))),
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ack_cmd.eq((port.cmd.valid & port.cmd.ready) | cmd_consumed),
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ack_wdata.eq((port.wdata.valid & port.wdata.ready) | wdata_consumed),
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ack_rdata.eq(port.rdata.valid & port.rdata.ready),
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]
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]
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# Read Datapath ----------------------------------------------------------------------------
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self.comb += [
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wishbone.dat_r.eq(port.rdata.data),
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]
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# Control ----------------------------------------------------------------------------------
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self.submodules.fsm = fsm = FSM(reset_state="CMD")
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fsm.act("CMD",
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port.flush.eq(~wishbone.cyc), # Flush write when transaction ends.
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port.cmd.last.eq(~wishbone.we), # Always wait for reads.
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port.cmd.valid.eq(wishbone.cyc & wishbone.stb),
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port.cmd.we.eq(wishbone.we),
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port.cmd.addr.eq(wishbone.adr - adr_offset),
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If(port.cmd.valid & port.cmd.ready,
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If(wishbone.we,
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NextState("WAIT-WRITE")
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).Else(
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NextState("WAIT-READ")
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)
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)
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)
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fsm.act("WAIT-WRITE",
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port.wdata.valid.eq(1),
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If(port.wdata.ready,
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wishbone.ack.eq(1),
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NextState("CMD")
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)
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)
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fsm.act("WAIT-READ",
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port.rdata.ready.eq(1),
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If(port.rdata.valid,
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wishbone.ack.eq(1),
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NextState("CMD")
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)
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)
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