Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy: Disable write_latency_calibration by default on Artix7 boards.

This commit is contained in:
Florent Kermarrec 2022-03-03 15:29:32 +01:00
parent c7d4d7f1b4
commit 4c1ce026e9
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litedram/phy/s7ddrphy.py
View File

@ -539,8 +539,8 @@ class K7DDRPHY(S7DDRPHY):
# Xilinx Artix7 (S7DDRPHY without odelay, sys2/4x_dqs generated in CRG with 90° phase vs sys2/4x) --
class A7DDRPHY(S7DDRPHY):
def __init__(self, pads, **kwargs):
S7DDRPHY.__init__(self, pads, with_odelay=False, **kwargs)
def __init__(self, pads, write_latency_calibration=False, **kwargs):
S7DDRPHY.__init__(self, pads, with_odelay=False, write_latency_calibration=write_latency_calibration, **kwargs)
def s7ddrphy_with_ratio(ratio, phy_cls=A7DDRPHY, ddr_clk=None, serdes_reset_cnt=0):