litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)
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b1f087959b
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4d19620a37
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@ -3,7 +3,6 @@
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{
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{
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# General ------------------------------------------------------------------
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -1, # FPGA speedgrade
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"speedgrade": -1, # FPGA speedgrade
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"memtype": "DDR3", # DRAM type
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"memtype": "DDR3", # DRAM type
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@ -3,7 +3,6 @@
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{
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{
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# General ------------------------------------------------------------------
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -2, # FPGA speedgrade
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"speedgrade": -2, # FPGA speedgrade
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"memtype": "DDR3", # DRAM type
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"memtype": "DDR3", # DRAM type
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@ -3,7 +3,6 @@
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{
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{
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# General ------------------------------------------------------------------
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -1, # FPGA speedgrade
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"speedgrade": -1, # FPGA speedgrade
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"memtype": "DDR2", # DRAM type
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"memtype": "DDR2", # DRAM type
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@ -3,8 +3,8 @@
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{
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{
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# General ------------------------------------------------------------------
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# General ------------------------------------------------------------------
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"platform": "ecp5", # Platform type
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"cpu": None, # Type of CPU used for init/calib (vexriscv, lm32)
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"cpu": None, # Type of CPU used for init/calib (vexriscv, lm32)
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"memtype": "DDR3", # DRAM type
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# PHY ----------------------------------------------------------------------
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# PHY ----------------------------------------------------------------------
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"sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM
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@ -32,6 +32,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.xilinx import XilinxPlatform
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from litex.build.lattice import LatticePlatform
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from litex.boards.platforms import versa_ecp5
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from litex.boards.platforms import versa_ecp5
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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@ -43,6 +44,8 @@ from litex.soc.cores.uart import *
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from litedram import modules as litedram_modules
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from litedram import modules as litedram_modules
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from litedram import phy as litedram_phys
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from litedram import phy as litedram_phys
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from litedram.phy.ecp5ddrphy import ECP5DDRPHY
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from litedram.phy.s7ddrphy import S7DDRPHY
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from litedram.core.controller import ControllerSettings
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from litedram.core.controller import ControllerSettings
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from litedram.frontend.axi import *
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from litedram.frontend.axi import *
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from litedram.frontend.wishbone import *
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from litedram.frontend.wishbone import *
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@ -336,28 +339,21 @@ class LiteDRAMCore(SoCSDRAM):
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**kwargs)
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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self.submodules.crg = crg = LatticeDRAMCRG(platform, core_config)
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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self.submodules.crg = LiteDRAMCRG(platform, core_config)
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if core_config["platform"] == "ecp5":
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# DRAM -------------------------------------------------------------------------------------
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crg = LatticeDRAMCRG(platform, core_config)
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platform.add_extension(get_dram_ios(core_config))
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self.submodules.crg = crg
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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assert core_config["memtype"] in ["DDR3"]
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self.submodules.ddrphy = core_config["sdram_phy"](
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self.submodules.ddrphy = core_config["sdram_phy"](
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platform.request("ddram"),
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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controller_settings = controller_settings=ControllerSettings(
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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controller_settings=controller_settings)
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else:
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self.submodules.crg = LiteDRAMCRG(platform, core_config)
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# DRAM -------------------------------------------------------------------------------------
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platform.add_extension(get_dram_ios(core_config))
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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self.submodules.ddrphy = core_config["sdram_phy"](
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self.submodules.ddrphy = core_config["sdram_phy"](
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platform.request("ddram"),
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platform.request("ddram"),
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@ -372,14 +368,16 @@ class LiteDRAMCore(SoCSDRAM):
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rtt_nom=core_config["rtt_nom"],
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rtt_nom=core_config["rtt_nom"],
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rtt_wr=core_config["rtt_wr"],
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rtt_wr=core_config["rtt_wr"],
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ron=core_config["ron"])
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ron=core_config["ron"])
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sdram_module = core_config["sdram_module"](sys_clk_freq,
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"1:4" if core_config["memtype"] == "DDR3" else "1:2")
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controller_settings = controller_settings=ControllerSettings(
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sdram_module = core_config["sdram_module"](sys_clk_freq,
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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"1:4" if core_config["memtype"] == "DDR3" else "1:2")
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self.register_sdram(self.ddrphy,
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controller_settings = controller_settings=ControllerSettings(
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sdram_module.geom_settings,
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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sdram_module.timing_settings,
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self.register_sdram(self.ddrphy,
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controller_settings=controller_settings)
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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controller_settings=controller_settings)
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# DRAM Initialization ----------------------------------------------------------------------
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# DRAM Initialization ----------------------------------------------------------------------
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self.submodules.ddrctrl = LiteDRAMCoreControl()
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self.submodules.ddrctrl = LiteDRAMCoreControl()
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@ -565,13 +563,12 @@ def main():
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core_config[k] = getattr(litedram_phys, core_config[k])
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core_config[k] = getattr(litedram_phys, core_config[k])
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# Generate core --------------------------------------------------------------------------------
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# Generate core --------------------------------------------------------------------------------
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platform = Platform()
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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if core_config["platform"] == "ecp5":
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platform = versa_ecp5.Platform(toolchain="trellis")
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platform = versa_ecp5.Platform(toolchain="trellis")
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elif core_config["platform"] == "xilinx":
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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platform = XilinxPlatform("", io=[], toolchain="vivado")
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platform = XilinxPlatform("", io=[], toolchain="vivado")
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else:
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else:
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raise ValueError("Unknown platform specified in {}".format(args.config));
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raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, integrated_sram_size=0x1000)
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, integrated_sram_size=0x1000)
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builder = Builder(soc, output_dir="build", compile_gateware=False)
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builder = Builder(soc, output_dir="build", compile_gateware=False)
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