init: add LPDDR4 initialization
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Jędrzej Boczar
parent
788b3f6d02
commit
4d9106847f
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@ -18,12 +18,13 @@ from litex.soc.interconnect import stream
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# Helpers ------------------------------------------------------------------------------------------
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burst_lengths = {
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"SDR": 1,
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"DDR": 4,
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"LPDDR": 4,
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"DDR2": 4,
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"DDR3": 8,
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"DDR4": 8
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"SDR": 1,
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"DDR": 4,
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"LPDDR": 4,
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"DDR2": 4,
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"DDR3": 8,
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"DDR4": 8,
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"LPDDR4": 16,
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}
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def get_default_cl_cwl(memtype, tck):
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136
litedram/init.py
136
litedram/init.py
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@ -445,16 +445,135 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
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return init_sequence, {1: mr1}
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# LPDDR4 -------------------------------------------------------------------------------------------
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def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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cwl = phy_settings.cwl
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bl = 16
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# TODO: on-die termination values
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dq_odt = "disable"
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ca_odt = "disable"
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def get_nwr():
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frequency_ranges = [ # Table 28. Frequency Ranges for RL, WL, nWR, and nRTP Settings
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# RL (DBI) WL (set) nWR nRTP frequency
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# w/o w/ A B > <=
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[( 6, 6), ( 4, 4), 6, 8, ( 10, 266)],
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[(10, 12), ( 6, 8), 10, 8, ( 266, 533)],
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[(14, 16), ( 8, 12), 16, 8, ( 533, 800)],
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[(20, 22), (10, 18), 20, 8, ( 800, 1066)],
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[(24, 28), (12, 22), 24, 10, (1066, 1333)],
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[(28, 32), (14, 26), 30, 12, (1333, 1600)],
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[(32, 36), (16, 30), 34, 14, (1600, 1866)],
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[(36, 40), (18, 34), 40, 16, (1866, 2133)],
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]
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# We use no DBI and WL set A
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for (rl, _), (wl, _), nwr, nrtp, (fmin, fmax) in frequency_ranges:
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if rl == cl:
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assert wl == cwl, "Wrong (RL, WL) combination"
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return nwr
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nwr = get_nwr()
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def reg(fields):
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regval = 0
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written = 0
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for shift, width, val in fields:
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mask = (2**width - 1) << shift
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assert written & mask == 0, "Would overwrite another field, xor=0b{:032b}".format(mask ^ written)
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assert val < 2**width, "Value larger than field width: val={}, width={}".format(val, width)
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regval |= (val << shift) & mask
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written |= mask
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return regval
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mr = {}
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mr[1] = reg([
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(0, 2, {16: 0b00, 32: 0b01, "on-the-fly": 0b10}[bl]),
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(2, 1, 1), # 2tCK WR preamble
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(3, 1, 0), # static RD preamble
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(4, 3, {
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6: 0b000,
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10: 0b001,
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16: 0b010,
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20: 0b011,
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24: 0b100,
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30: 0b101,
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34: 0b110,
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40: 0b111,
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}[nwr]),
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(7, 1, 0), # 0.5tCK RD postamble
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])
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mr[2] = reg([
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(0, 3, { # RL assuming DBI-RD disabled
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6: 0b000,
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10: 0b001,
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14: 0b010,
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20: 0b011,
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24: 0b100,
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28: 0b101,
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32: 0b110,
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36: 0b111,
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}[cl]),
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(3, 3, { # WL, set A
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4: 0b000,
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6: 0b001,
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8: 0b010,
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10: 0b011,
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12: 0b100,
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14: 0b101,
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16: 0b110,
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18: 0b111,
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}[cwl]),
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(6, 1, 0), # use set A
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(7, 1, 0), # write leveling disabled
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])
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# MR3 - defaults (DBI disabled)
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odt_map = {
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"disable": 0b000,
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"RZQ/1": 0b001,
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"RZQ/2": 0b010,
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"RZQ/3": 0b011,
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"RZQ/4": 0b100,
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"RZQ/5": 0b101,
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"RZQ/6": 0b110,
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}
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mr[11] = reg([
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(0, 3, odt_map[dq_odt]),
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(4, 3, odt_map[ca_odt]),
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])
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# MR12, MR14 - default Vref 50.3% Vddq
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# MR13 - defaults (data mask enabled)
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def cmd_mr(ma):
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# Convert Mode Register Write command to DFI as expected by PHY
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op = mr[ma]
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assert ma < 2**6, "MR address to big: {}".format(ma)
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assert op < 2**8, "MR opcode to big: {}".format(op)
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a = op | (ma << 8)
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ba = 0
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return ("Load More Register {}".format(ma), a, ba, cmds["MODE_REGISTER"], 200)
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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*[cmd_mr(ma) for ma in sorted(mr.keys())],
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# TODO: ZQ calibration
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]
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return init_sequence, mr
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# Init Sequence ------------------------------------------------------------------------------------
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def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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return {
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"SDR" : get_sdr_phy_init_sequence,
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"DDR" : get_ddr_phy_init_sequence,
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"LPDDR": get_lpddr_phy_init_sequence,
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"DDR2" : get_ddr2_phy_init_sequence,
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"DDR3" : get_ddr3_phy_init_sequence,
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"DDR4" : get_ddr4_phy_init_sequence,
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"SDR": get_sdr_phy_init_sequence,
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"DDR": get_ddr_phy_init_sequence,
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"LPDDR": get_lpddr_phy_init_sequence,
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"DDR2": get_ddr2_phy_init_sequence,
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"DDR3": get_ddr3_phy_init_sequence,
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"DDR4": get_ddr4_phy_init_sequence,
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"LPDDR4": get_lpddr4_phy_init_sequence,
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}[phy_settings.memtype](phy_settings, timing_settings)
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# C Header -----------------------------------------------------------------------------------------
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@ -573,6 +692,11 @@ const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {{
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r += "#define DDRX_MR_WRLVL_ADDRESS {}\n".format(1)
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r += "#define DDRX_MR_WRLVL_RESET {}\n".format(mr[1])
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r += "#define DDRX_MR_WRLVL_BIT {}\n\n".format(7)
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elif phy_settings.memtype in ["LPDDR4"]:
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# Write leveling enabled by MR2[7]
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r += "#define DDRX_MR_WRLVL_ADDRESS {}\n".format(2)
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r += "#define DDRX_MR_WRLVL_RESET {}\n".format(mr[2])
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r += "#define DDRX_MR_WRLVL_BIT {}\n\n".format(7)
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r += "static void init_sequence(void)\n{\n"
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for comment, a, ba, cmd, delay in init_sequence:
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