test: split test_fifo_ctrl into 2 separate tests
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@ -19,6 +19,7 @@ from test.common import *
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class TestFIFO(unittest.TestCase):
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@passive
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def fifo_ctrl_flag_checker(self, fifo_ctrl, write_threshold, read_threshold):
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# checks the combinational logic
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while True:
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level = (yield fifo_ctrl.level)
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self.assertEqual((yield fifo_ctrl.writable), level < write_threshold)
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@ -27,15 +28,14 @@ class TestFIFO(unittest.TestCase):
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# _LiteDRAMFIFOCtrl ----------------------------------------------------------------------------
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def test_fifo_ctrl(self):
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def test_fifo_ctrl_address_changes(self):
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# we are ignoring thresholds (so readable/writable signals)
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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def main_generator():
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self.assertEqual((yield dut.level), 0)
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self.assertEqual((yield dut.write_address), 0)
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self.assertEqual((yield dut.read_address), 0)
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# ignore readable/writable
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# write address
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yield dut.write.eq(1)
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yield
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@ -57,6 +57,18 @@ class TestFIFO(unittest.TestCase):
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yield
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self.assertEqual((yield dut.read_address), 24 % 16)
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generators = [
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main_generator(),
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self.fifo_ctrl_flag_checker(dut, write_threshold=16, read_threshold=0),
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]
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run_simulation(dut, generators)
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def test_fifo_ctrl_level_changes(self):
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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def main_generator():
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self.assertEqual((yield dut.level), 0)
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# level
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def check_level_diff(write, read, diff):
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level = (yield dut.level)
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@ -68,8 +80,11 @@ class TestFIFO(unittest.TestCase):
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yield
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self.assertEqual((yield dut.level), level + diff)
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check_level_diff(write=1, read=0, diff=+1)
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check_level_diff(write=1, read=0, diff=+1)
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check_level_diff(write=1, read=1, diff=+0)
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check_level_diff(write=1, read=1, diff=+0)
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check_level_diff(write=0, read=1, diff=-1)
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check_level_diff(write=0, read=1, diff=-1)
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generators = [
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