bench: add DDR4 Mode Register settings generator.
Useful to change timing/electrical settings dynamically and bringup/debug DDR4 on new hardware.
This commit is contained in:
Florent Kermarrec
parent
db54e325c8
commit
5257197475
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#!/usr/bin/env python3
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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parser = argparse.ArgumentParser(description="DDR4 Mode Register settings generator for LiteDRAM.")
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parser.add_argument("--list", action="store_true", help="List supported DDR4 settings.")
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parser.add_argument("--cl", default="11", help="CAS Latency.")
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parser.add_argument("--cwl", default="9", help="CAS Write Latency.")
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parser.add_argument("--rtt_nom", default="40ohm", help="RTT_NOM value.")
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parser.add_argument("--rtt_wr", default="120ohm", help="RTT_WR value.")
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parser.add_argument("--ron", default="34ohm", help="RON value.")
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args = parser.parse_args()
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# DDR4 Timing settings -----------------------------------------------------------------------------
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cl_to_mr0 = {
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9: 0b00000,
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10: 0b00001,
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11: 0b00010,
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12: 0b00011,
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13: 0b00100,
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14: 0b00101,
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15: 0b00110,
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16: 0b00111,
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18: 0b01000,
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20: 0b01001,
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22: 0b01010,
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24: 0b01011,
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23: 0b01100,
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17: 0b01101,
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19: 0b01110,
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21: 0b01111,
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25: 0b10000,
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26: 0b10001,
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27: 0b10010,
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28: 0b10011,
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29: 0b10100,
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30: 0b10101,
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31: 0b10110,
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32: 0b10111,
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}
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cwl_to_mr2 = {
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9: 0b000,
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10: 0b001,
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11: 0b010,
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12: 0b011,
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14: 0b100,
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16: 0b101,
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18: 0b110,
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20: 0b111
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}
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if args.list:
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print("Supported DDR4 Timing settings:")
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print("cl:")
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for v in cl_to_mr0.keys():
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print(f" - {v}")
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print("cwl:")
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for v in cwl_to_mr2.keys():
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print(f" - {v}")
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# DDR4 Electrical settings -------------------------------------------------------------------------
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z_to_rtt_nom = {
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"disabled" : 0b000,
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"60ohm" : 0b001,
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"120ohm" : 0b010,
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"40ohm" : 0b011,
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"240ohm" : 0b100,
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"48ohm" : 0b101,
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"80ohm" : 0b110,
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"34ohm" : 0b111
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}
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z_to_rtt_wr = {
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"disabled" : 0b000,
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"120ohm" : 0b001,
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"240ohm" : 0b010,
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"high-z" : 0b011,
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"80ohm" : 0b100,
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}
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z_to_ron = {
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"34ohm" : 0b00,
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"48ohm" : 0b01,
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}
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if args.list:
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print("Supported DDR4 Electrical settings:")
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print("rtt_nom:")
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for v in z_to_rtt_nom.keys():
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print(f" - {v}")
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print("rtt_wr:")
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for v in z_to_rtt_wr.keys():
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print(f" - {v}")
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print("ron:")
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for v in z_to_ron.keys():
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print(f" - {v}")
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# DDR4 Mode Register formating ---------------------------------------------------------------------
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if args.list:
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exit()
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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wr_to_mr0 = {
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10: 0b0000,
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12: 0b0001,
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14: 0b0010,
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16: 0b0011,
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18: 0b0100,
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20: 0b0101,
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24: 0b0110,
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22: 0b0111,
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26: 0b1000,
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28: 0b1001,
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 0b1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= ((cl_to_mr0[cl] >> 4) & 0b1) << 12
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mr0 |= dll_reset << 8
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mr0 |= (wr_to_mr0[wr] & 0b111) << 9
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mr0 |= (wr_to_mr0[wr] >> 3) << 13
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return mr0
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def format_mr1(dll_enable, ron, rtt_nom):
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mr1 = dll_enable
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mr1 |= ((ron >> 0) & 0b1) << 1
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mr1 |= ((ron >> 1) & 0b1) << 2
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mr1 |= ((rtt_nom >> 0) & 0b1) << 8
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mr1 |= ((rtt_nom >> 1) & 0b1) << 9
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mr1 |= ((rtt_nom >> 2) & 0b1) << 10
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return mr1
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def format_mr2(cwl, rtt_wr):
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mr2 = cwl_to_mr2[cwl] << 3
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mr2 |= rtt_wr << 9
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return mr2
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print("DDR4 Timing Settings:")
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print(f"cl: {args.cl}")
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print(f"cwl: {args.cwl}")
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print("DDR4 Electrical Settings:")
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print(f"rtt_nom: {args.rtt_nom}")
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print(f"rtt_wr: {args.rtt_wr}")
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print(f"ron: {args.ron}")
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print("Commands to be used with LiteX BIOS:")
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print("sdram_mr_write 0 {:d}".format(format_mr0(
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bl = 8,
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cl = int(args.cl, 0),
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wr = 10,
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dll_reset = 0))
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)
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print("sdram_mr_write 1 {:d}".format(format_mr1(
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dll_enable = 1,
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ron = z_to_ron[args.ron],
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rtt_nom = z_to_rtt_nom[args.rtt_nom]))
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)
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print("sdram_mr_write 2 {:d}".format(format_mr2(
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cwl = int(args.cwl, 0),
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rtt_wr = z_to_rtt_wr[args.rtt_wr]))
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)
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