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litedram_gen: cleanup ident/align, use dynamic CSRs.

This commit is contained in:
Florent Kermarrec 2020-02-20 09:20:11 +01:00
parent f1dba787f6
commit 53d3a0a9c2
1 changed files with 29 additions and 34 deletions
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19
litedram/gen.py
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@ -306,11 +306,6 @@ class LiteDRAMCoreControl(Module, AutoCSR):
# LiteDRAMCore -------------------------------------------------------------------------------------
class LiteDRAMCore(SoCSDRAM):
csr_map = {
"ddrctrl": 16,
"ddrphy": 17
}
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
@ -349,14 +344,14 @@ class LiteDRAMCore(SoCSDRAM):
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
assert core_config["memtype"] in ["DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
platform.request("ddram"),
pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
platform.request("ddram"),
pads = platform.request("ddram"),
memtype = core_config["memtype"],
nphases = 4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq = sys_clk_freq,
@ -368,19 +363,20 @@ class LiteDRAMCore(SoCSDRAM):
rtt_nom = core_config["rtt_nom"],
rtt_wr = core_config["rtt_wr"],
ron = core_config["ron"])
self.add_csr("ddrphy")
sdram_module = core_config["sdram_module"](sys_clk_freq,
"1:4" if core_config["memtype"] == "DDR3" else "1:2")
controller_settings = controller_settings=ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings,
controller_settings = controller_settings)
# DRAM Initialization ----------------------------------------------------------------------
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
self.comb += [
platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage)
@ -392,8 +388,7 @@ class LiteDRAMCore(SoCSDRAM):
address_width = self.csr_address_width,
data_width = self.csr_data_width)
self.add_csr_master(csr_port)
platform.add_extension(get_csr_ios(self.csr_address_width,
self.csr_data_width))
platform.add_extension(get_csr_ios(self.csr_address_width, self.csr_data_width))
_csr_port_io = platform.request("csr_port", 0)
self.comb += [
csr_port.adr.eq(_csr_port_io.adr),