phy/ecp5ddrphy: remplace dq_i DELAYF with DELAYG.
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@ -349,13 +349,10 @@ class ECP5DDRPHY(Module, AutoCSR):
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cycles = 1)
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self.submodules += dq_i_bitslip
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self.specials += [
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Instance("DELAYF",
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p_DEL_MODE = "DQS_ALIGNED_X2",
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i_LOADN = 0,
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i_MOVE = 0,
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i_DIRECTION = 0,
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i_A = dq_i,
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o_Z = dq_i_delayed
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Instance("DELAYG",
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p_DEL_MODE = "DQS_ALIGNED_X2",
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i_A = dq_i,
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o_Z = dq_i_delayed
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),
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Instance("IDDRX2DQA",
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i_RST = ResetSignal("sys"),
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