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bench/common: enable load_rom on kcu105 (with delay workaround).

This commit is contained in:
Florent Kermarrec 2020-09-03 17:46:50 +02:00
parent 41c8ac637d
commit 543a94dd33
1 changed files with 5 additions and 2 deletions
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7
bench/common.py
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@ -4,6 +4,8 @@
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import time
# PLL Helpers -------------------------------------------------------------------------------------- # PLL Helpers --------------------------------------------------------------------------------------
class ClkReg1: class ClkReg1:
@ -97,11 +99,12 @@ class BenchController:
def reboot(self): def reboot(self):
self.bus.regs.ctrl_reset.write(1) self.bus.regs.ctrl_reset.write(1)
def load_rom(self, filename): def load_rom(self, filename, delay=0):
from litex.soc.integration.common import get_mem_data from litex.soc.integration.common import get_mem_data
rom_data = get_mem_data(filename, "little") rom_data = get_mem_data(filename, "little")
for i, data in enumerate(rom_data): for i, data in enumerate(rom_data):
self.bus.write(self.bus.mems.rom.base + 4*i, data) self.bus.write(self.bus.mems.rom.base + 4*i, data)
time.sleep(delay)
# Bench Test --------------------------------------------------------------------------------------- # Bench Test ---------------------------------------------------------------------------------------
@ -182,7 +185,7 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
# Load BIOS and reboot SoC # Load BIOS and reboot SoC
ctrl = BenchController(bus) ctrl = BenchController(bus)
#ctrl.load_rom(bios_filename) ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed on KCU105 @ 11200bauds.
ctrl.reboot() ctrl.reboot()
# PLL/ClkReg # PLL/ClkReg