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phy/gw2ddrphy: Minor cosmetic cleanups.

This commit is contained in:
Florent Kermarrec 2022-09-08 16:09:38 +02:00
parent cff8500f52
commit 559dd24c99
1 changed files with 67 additions and 73 deletions
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14
litedram/phy/gw2ddrphy.py
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@ -381,8 +381,7 @@ class GW2DDRPHY(Module, AutoCSR):
dq_bl8_cases[0] = dq_o_data_muxed.eq(dq_o_data[:4]) dq_bl8_cases[0] = dq_o_data_muxed.eq(dq_o_data[:4])
dq_bl8_cases[1] = dq_o_data_muxed.eq(dq_o_data_d[4:]) dq_bl8_cases[1] = dq_o_data_muxed.eq(dq_o_data_d[4:])
self.sync += Case(bl8_chunk, dq_bl8_cases) self.sync += Case(bl8_chunk, dq_bl8_cases)
self.specials += [ self.specials += Instance("OSER4_MEM",
Instance("OSER4_MEM",
p_TCLK_SOURCE = "DQSW270", p_TCLK_SOURCE = "DQSW270",
p_TXCLK_POL = 0b0, p_TXCLK_POL = 0b0,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
@ -394,15 +393,13 @@ class GW2DDRPHY(Module, AutoCSR):
**{f"i_D{n}": dq_o_data_muxed[n] for n in range(4)}, **{f"i_D{n}": dq_o_data_muxed[n] for n in range(4)},
o_Q0 = dq_o, o_Q0 = dq_o,
o_Q1 = dq_o_oen, o_Q1 = dq_o_oen,
), )
]
dq_i_bitslip = BitSlip(4, dq_i_bitslip = BitSlip(4,
rst = self._dly_sel.storage[i] & self._rdly_dq_bitslip_rst.re, rst = self._dly_sel.storage[i] & self._rdly_dq_bitslip_rst.re,
slp = self._dly_sel.storage[i] & self._rdly_dq_bitslip.re, slp = self._dly_sel.storage[i] & self._rdly_dq_bitslip.re,
cycles = 1) cycles = 1)
self.submodules += dq_i_bitslip self.submodules += dq_i_bitslip
self.specials += [ self.specials += Instance("IDES4_MEM",
Instance("IDES4_MEM",
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),
@ -413,20 +410,17 @@ class GW2DDRPHY(Module, AutoCSR):
i_CALIB = 0, i_CALIB = 0,
**{f"o_Q{n}": dq_i_bitslip.i[n] for n in range(4)}, **{f"o_Q{n}": dq_i_bitslip.i[n] for n in range(4)},
) )
]
dq_i_bitslip_o_d = Signal(4) dq_i_bitslip_o_d = Signal(4)
self.sync += dq_i_bitslip_o_d.eq(dq_i_bitslip.o) self.sync += dq_i_bitslip_o_d.eq(dq_i_bitslip.o)
self.comb += dq_i_data.eq(Cat(dq_i_bitslip_o_d, dq_i_bitslip.o)) self.comb += dq_i_data.eq(Cat(dq_i_bitslip_o_d, dq_i_bitslip.o))
for n in range(8): for n in range(8):
self.comb += dfi.phases[n//4].rddata[n%4*databits+j].eq(dq_i_data[n]) self.comb += dfi.phases[n//4].rddata[n%4*databits+j].eq(dq_i_data[n])
self.specials += [ self.specials += Instance("IOBUF",
Instance("IOBUF",
i_I = dq_o, i_I = dq_o,
i_OEN = dq_o_oen, i_OEN = dq_o_oen,
o_O = dq_i, o_O = dq_i,
io_IO = pads.dq[j] io_IO = pads.dq[j]
) )
]
# Read Control Path ------------------------------------------------------------------------ # Read Control Path ------------------------------------------------------------------------
rdtap = cl_sys_latency # CHECKME: Latency. rdtap = cl_sys_latency # CHECKME: Latency.