test: fix quotes
This commit is contained in:
Jędrzej Boczar
parent
ef9b13d7e8
commit
5618d2a54c
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@ -3,7 +3,6 @@
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# License: BSD
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import unittest
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import random
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from migen import *
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@ -89,14 +88,14 @@ class TestBIST(unittest.TestCase):
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def setUp(self):
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# define common test data used for both generator and checker tests
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self.bist_test_data = {
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'8bit': dict(
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"8bit": dict(
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base = 2,
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end = 2 + 8, # (end - base) must be pow of 2
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length = 5,
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# 2 3 4 5 6 7=2+5
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expected = [0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x00],
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),
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'32bit': dict(
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"32bit": dict(
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base = 0x04,
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end = 0x04 + 8,
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length = 5 * 4,
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@ -111,7 +110,7 @@ class TestBIST(unittest.TestCase):
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0x00000000, # 0x1c
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],
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),
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'64bit': dict(
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"64bit": dict(
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base = 0x10,
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end = 0x10 + 8,
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length = 5 * 8,
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@ -126,7 +125,7 @@ class TestBIST(unittest.TestCase):
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0x0000000000000000, # 0x38
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],
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),
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'32bit_masked': dict(
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"32bit_masked": dict(
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base = 0x04,
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end = 0x04 + 0x04, # TODO: fix address masking to be consistent
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length = 6 * 4,
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@ -142,17 +141,17 @@ class TestBIST(unittest.TestCase):
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],
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),
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}
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self.bist_test_data['32bit_long_sequential'] = dict(
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self.bist_test_data["32bit_long_sequential"] = dict(
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base = 16,
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end = 16 + 128,
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length = 64,
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expected = [0x00000000] * 128
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)
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expected = self.bist_test_data['32bit_long_sequential']['expected']
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expected = self.bist_test_data["32bit_long_sequential"]["expected"]
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expected[16//4:(16 + 64)//4] = list(range(64//4))
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self.pattern_test_data = {
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'8bit': dict(
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"8bit": dict(
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pattern = [
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# address, data
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(0x00, 0xaa),
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@ -172,7 +171,7 @@ class TestBIST(unittest.TestCase):
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0xdd, # 0x07
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],
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),
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'32bit': dict(
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"32bit": dict(
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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@ -192,7 +191,7 @@ class TestBIST(unittest.TestCase):
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0xbaadf00d, # 0x1c
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],
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),
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'64bit': dict(
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"64bit": dict(
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pattern = [
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# address, data
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(0x00, 0x0ddf00dbadc0ffee),
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@ -212,7 +211,7 @@ class TestBIST(unittest.TestCase):
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0xdeadc0debaadbeef, # 0x38
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],
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),
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'32bit_not_aligned': dict(
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"32bit_not_aligned": dict(
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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@ -232,7 +231,7 @@ class TestBIST(unittest.TestCase):
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0xbaadf00d, # 0x1c
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],
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),
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'32bit_duplicates': dict(
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"32bit_duplicates": dict(
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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@ -252,7 +251,7 @@ class TestBIST(unittest.TestCase):
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0xdeadc0de, # 0x1c
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],
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),
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'32bit_sequential': dict(
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"32bit_sequential": dict(
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pattern = [
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# address, data
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(0x02, 0xabadcafe),
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@ -275,8 +274,6 @@ class TestBIST(unittest.TestCase):
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}
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def test_generator(self):
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port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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def main_generator(dut):
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self.errors = 0
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@ -310,7 +307,7 @@ class TestBIST(unittest.TestCase):
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self.assertEqual(self.errors, 0)
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def generator_test(self, mem_expected, data_width, pattern=None, config_args=None, check_mem=True):
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assert pattern is None or config_args is None, '_LiteDRAMBISTGenerator xor _LiteDRAMPatternGenerator'
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assert pattern is None or config_args is None, "_LiteDRAMBISTGenerator xor _LiteDRAMPatternGenerator"
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class DUT(Module):
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def __init__(self):
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@ -339,8 +336,8 @@ class TestBIST(unittest.TestCase):
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return dut
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def test_bist_generator_8bit(self):
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data = self.bist_test_data['8bit']
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self.generator_test(data.pop('expected'), data_width=8, config_args=data)
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data = self.bist_test_data["8bit"]
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self.generator_test(data.pop("expected"), data_width=8, config_args=data)
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def test_bist_generator_range_must_be_pow2(self):
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# NOTE:
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@ -348,73 +345,73 @@ class TestBIST(unittest.TestCase):
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# but it would be better if this restriction didn't hold, this test
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# is here just to notice the change if it happens unintentionally
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# and may be removed if we start supporting arbitrary ranges
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data = self.bist_test_data['8bit']
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data['end'] += 1
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reference = data.pop('expected')
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data = self.bist_test_data["8bit"]
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data["end"] += 1
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reference = data.pop("expected")
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dut = self.generator_test(reference, data_width=8, config_args=data, check_mem=False)
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self.assertNotEqual(dut.mem.mem, reference)
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def test_bist_generator_32bit(self):
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data = self.bist_test_data['32bit']
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self.generator_test(data.pop('expected'), data_width=32, config_args=data)
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data = self.bist_test_data["32bit"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_64bit(self):
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data = self.bist_test_data['64bit']
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self.generator_test(data.pop('expected'), data_width=64, config_args=data)
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data = self.bist_test_data["64bit"]
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self.generator_test(data.pop("expected"), data_width=64, config_args=data)
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def test_bist_generator_32bit_address_masked(self):
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data = self.bist_test_data['32bit_masked']
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self.generator_test(data.pop('expected'), data_width=32, config_args=data)
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data = self.bist_test_data["32bit_masked"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_32bit_long_sequential(self):
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data = self.bist_test_data['32bit_long_sequential']
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self.generator_test(data.pop('expected'), data_width=32, config_args=data)
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data = self.bist_test_data["32bit_long_sequential"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_random_data(self):
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data = self.bist_test_data['32bit']
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data['random_data'] = True
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dut = self.generator_test(data.pop('expected'), data_width=32, config_args=data, check_mem=False)
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data = self.bist_test_data["32bit"]
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data["random_data"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data, check_mem=False)
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# only check that there are no duplicates and that data is not a simple sequence
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mem = [val for val in dut.mem.mem if val != 0]
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self.assertEqual(len(set(mem)), len(mem), msg='Duplicate values in memory')
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self.assertNotEqual(mem, list(range(len(mem))), msg='Values are a sequence')
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self.assertEqual(len(set(mem)), len(mem), msg="Duplicate values in memory")
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self.assertNotEqual(mem, list(range(len(mem))), msg="Values are a sequence")
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def test_bist_generator_random_addr(self): # write whole memory and check if there are no repetitions?
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data = self.bist_test_data['32bit']
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data['random_addr'] = True
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dut = self.generator_test(data.pop('expected'), data_width=32, config_args=data, check_mem=False)
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data = self.bist_test_data["32bit"]
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data["random_addr"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data, check_mem=False)
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# with random address and address wrapping (generator.end) we _can_ have duplicates
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# we can at least check that the values written are not an ordered sequence
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mem = [val for val in dut.mem.mem if val != 0]
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self.assertNotEqual(mem, list(range(len(mem))), msg='Values are a sequence')
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self.assertLess(max(mem), data['length'], msg='Too big value found')
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self.assertNotEqual(mem, list(range(len(mem))), msg="Values are a sequence")
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self.assertLess(max(mem), data["length"], msg="Too big value found")
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def test_pattern_generator_8bit(self):
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data = self.pattern_test_data['8bit']
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self.generator_test(data['expected'], data_width=8, pattern=data['pattern'])
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data = self.pattern_test_data["8bit"]
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self.generator_test(data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_generator_32bit(self):
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data = self.pattern_test_data['32bit']
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self.generator_test(data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_64bit(self):
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data = self.pattern_test_data['64bit']
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self.generator_test(data['expected'], data_width=64, pattern=data['pattern'])
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data = self.pattern_test_data["64bit"]
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self.generator_test(data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_generator_32bit_not_aligned(self):
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data = self.pattern_test_data['32bit_not_aligned']
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self.generator_test(data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit_not_aligned"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_duplicates(self):
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data = self.pattern_test_data['32bit_duplicates']
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self.generator_test(data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit_duplicates"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_sequential(self):
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data = self.pattern_test_data['32bit_sequential']
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self.generator_test(data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit_sequential"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def checker_test(self, memory, data_width, pattern=None, config_args=None, check_errors=False):
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assert pattern is None or config_args is None, '_LiteDRAMBISTChecker xor _LiteDRAMPatternChecker'
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assert pattern is None or config_args is None, "_LiteDRAMBISTChecker xor _LiteDRAMPatternChecker"
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class DUT(Module):
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def __init__(self):
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@ -444,40 +441,41 @@ class TestBIST(unittest.TestCase):
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return dut, checker
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def test_bist_checker_8bit(self):
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data = self.bist_test_data['8bit']
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memory = data.pop('expected')
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data = self.bist_test_data["8bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=8, config_args=data)
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def test_bist_checker_32bit(self):
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data = self.bist_test_data['32bit']
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memory = data.pop('expected')
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data = self.bist_test_data["32bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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def test_bist_checker_64bit(self):
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data = self.bist_test_data['32bit']
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memory = data.pop('expected')
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data = self.bist_test_data["32bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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def test_pattern_checker_8bit(self):
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data = self.pattern_test_data['8bit']
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self.checker_test(memory=data['expected'], data_width=8, pattern=data['pattern'])
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data = self.pattern_test_data["8bit"]
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self.checker_test(memory=data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_checker_32bit(self):
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data = self.pattern_test_data['32bit']
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self.checker_test(memory=data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_64bit(self):
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data = self.pattern_test_data['64bit']
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self.checker_test(memory=data['expected'], data_width=64, pattern=data['pattern'])
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data = self.pattern_test_data["64bit"]
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self.checker_test(memory=data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_checker_32bit_not_aligned(self):
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data = self.pattern_test_data['32bit_not_aligned']
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self.checker_test(memory=data['expected'], data_width=32, pattern=data['pattern'])
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data = self.pattern_test_data["32bit_not_aligned"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_32bit_duplicates(self):
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data = self.pattern_test_data['32bit_duplicates']
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num_duplicates = len(data['pattern']) - len(set(adr for adr, _ in data['pattern']))
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dut, checker = self.checker_test(memory=data['expected'], data_width=32, pattern=data['pattern'], check_errors=False)
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data = self.pattern_test_data["32bit_duplicates"]
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num_duplicates = len(data["pattern"]) - len(set(adr for adr, _ in data["pattern"]))
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dut, checker = self.checker_test(
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memory=data["expected"], data_width=32, pattern=data["pattern"], check_errors=False)
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self.assertEqual(checker.errors, num_duplicates)
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def bist_test(self, generator, checker, mem):
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@ -565,8 +563,8 @@ class TestBIST(unittest.TestCase):
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def test_bist_csr_cdc(self):
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32, clock_domain='async')
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32, clock_domain='async')
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32, clock_domain="async")
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32, clock_domain="async")
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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@ -580,16 +578,16 @@ class TestBIST(unittest.TestCase):
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mem = DRAMMemory(32, 48)
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generators = {
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'sys': [
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"sys": [
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main_generator(dut, mem),
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],
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'async': [
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"async": [
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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}
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clocks = {
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'sys': 10,
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'async': (7, 3),
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"sys": 10,
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"async": (7, 3),
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}
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run_simulation(dut, generators, clocks)
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