Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

frontend/dma: test and fix add_csr on DMAs

This commit is contained in:
Florent Kermarrec 2020-02-03 19:47:49 +01:00
parent c536330e36
commit 586980a4e5
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litedram/frontend/dma.py
View File

@ -47,6 +47,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
""" """
def __init__(self, port, fifo_depth=16, fifo_buffered=False): def __init__(self, port, fifo_depth=16, fifo_buffered=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.port = port self.port = port
self.sink = sink = stream.Endpoint([("address", port.address_width)]) self.sink = sink = stream.Endpoint([("address", port.address_width)])
self.source = source = stream.Endpoint([("data", port.data_width)]) self.source = source = stream.Endpoint([("data", port.data_width)])
@ -130,7 +131,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
self.sink.valid.eq(1), self.sink.valid.eq(1),
self.sink.address.eq(base + offset), self.sink.address.eq(base + offset),
If(self.sink.ready, If(self.sink.ready,
If(offset == (length-1), NextValue(offset, offset + 1),
If(offset == (length - 1),
If(self._loop.storage, If(self._loop.storage,
NextValue(offset, 0) NextValue(offset, 0)
).Else( ).Else(
@ -164,6 +166,7 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
""" """
def __init__(self, port, fifo_depth=16, fifo_buffered=False): def __init__(self, port, fifo_depth=16, fifo_buffered=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.port = port
self.sink = sink = stream.Endpoint([("address", port.address_width), self.sink = sink = stream.Endpoint([("address", port.address_width),
("data", port.data_width)]) ("data", port.data_width)])
@ -205,7 +208,7 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
def add_csr(self): def add_csr(self):
self._sink = self.sink self._sink = self.sink
self.sink = stream.Endpoint(("data", port.data_width)) self.sink = stream.Endpoint([("data", self.port.data_width)])
self._base = CSRStorage(32) self._base = CSRStorage(32)
self._length = CSRStorage(32) self._length = CSRStorage(32)
@ -238,7 +241,8 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
self._sink.address.eq(base + offset), self._sink.address.eq(base + offset),
self.sink.ready.eq(self._sink.ready), self.sink.ready.eq(self._sink.ready),
If(self.sink.ready, If(self.sink.ready,
If(offset == (length-1), NextValue(offset, offset + 1),
If(offset == (length - 1),
If(self._loop.storage, If(self._loop.storage,
NextValue(offset, 0) NextValue(offset, 0)
).Else( ).Else(