Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

frontend/bist: refactor(simplify) LiteDRAMBISTChecker

This commit is contained in:
Florent Kermarrec 2016-12-17 17:06:10 +01:00
parent 381789c84d
commit 5909e5d76e
1 changed files with 61 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

107
litedram/frontend/bist.py
View File

@ -53,7 +53,7 @@ class _LiteDRAMBISTGenerator(Module):
gen_cls = LFSR if random else Counter gen_cls = LFSR if random else Counter
self.submodules.gen = gen = gen_cls(dram_port.dw) self.submodules.gen = gen = gen_cls(dram_port.dw)
offset = Signal(dram_port.aw) cmd_counter = Signal(dram_port.aw)
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
self.submodules += fsm self.submodules += fsm
@ -61,7 +61,7 @@ class _LiteDRAMBISTGenerator(Module):
fsm.act("IDLE", fsm.act("IDLE",
self.done.eq(1), self.done.eq(1),
If(self.start, If(self.start,
NextValue(offset, 0), NextValue(cmd_counter, 0),
NextState("RUN") NextState("RUN")
) )
) )
@ -69,14 +69,14 @@ class _LiteDRAMBISTGenerator(Module):
dma.sink.valid.eq(1), dma.sink.valid.eq(1),
If(dma.sink.ready, If(dma.sink.ready,
gen.ce.eq(1), gen.ce.eq(1),
NextValue(offset, offset + 1), NextValue(cmd_counter, cmd_counter + 1),
If(offset == (self.length-1), If(cmd_counter == (self.length-1),
NextState("IDLE") NextState("IDLE")
) )
) )
) )
self.comb += [ self.comb += [
dma.sink.address.eq(self.base + offset), dma.sink.address.eq(self.base + cmd_counter),
dma.sink.data.eq(gen.o) dma.sink.data.eq(gen.o)
] ]
@ -129,63 +129,64 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.done = Signal() self.done = Signal()
self.base = Signal(dram_port.aw) self.base = Signal(dram_port.aw)
self.length = Signal(dram_port.aw) self.length = Signal(dram_port.aw)
self.error_count = Signal(32) self.err_count = Signal(32)
# # # # # #
self.submodules.dma = dma = LiteDRAMDMAReader(dram_port) self.submodules.dma = dma = LiteDRAMDMAReader(dram_port)
gen_cls = LFSR if random else Counter
self.submodules.gen = gen = gen_cls(dram_port.dw)
if random: # address
self.submodules.gen = gen = LFSR(dram_port.dw) cmd_counter = Signal(dram_port.aw)
else: cmd_fsm = FSM(reset_state="IDLE")
self.submodules.gen = gen = Counter(dram_port.dw) self.submodules += cmd_fsm
started = Signal() cmd_fsm.act("IDLE",
address_counter = Signal(dram_port.aw) If(self.start,
address_counter_ce = Signal() NextValue(cmd_counter, 0),
NextState("RUN")
)
)
cmd_fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (self.length-1),
NextState("IDLE")
)
)
)
self.comb += dma.sink.address.eq(self.base + cmd_counter)
# data
data_counter = Signal(dram_port.aw) data_counter = Signal(dram_port.aw)
data_counter_ce = Signal() data_fsm = FSM(reset_state="IDLE")
self.sync += [ self.submodules += data_fsm
data_fsm.act("IDLE",
If(self.start, If(self.start,
started.eq(1) NextValue(data_counter, 0),
), NextValue(self.err_count, 0),
If(self.start, NextState("RUN")
address_counter.eq(0)
).Elif(address_counter_ce,
address_counter.eq(address_counter + 1)
),
If(self.start,
data_counter.eq(0),
).Elif(data_counter_ce,
data_counter.eq(data_counter + 1)
) )
] )
data_fsm.act("RUN",
address_enable = Signal() dma.source.ready.eq(1),
self.comb += address_enable.eq(started & (address_counter != (self.length - 1)))
self.comb += [
dma.sink.valid.eq(address_enable),
dma.sink.address.eq(self.base + address_counter),
address_counter_ce.eq(address_enable & dma.sink.ready)
]
data_enable = Signal()
self.comb += data_enable.eq(started & (data_counter != (self.length - 1)))
self.comb += [
gen.ce.eq(dma.source.valid),
dma.source.ready.eq(1)
]
self.sync += \
If(dma.source.valid, If(dma.source.valid,
gen.ce.eq(1),
NextValue(data_counter, data_counter + 1),
If(dma.source.data != gen.o, If(dma.source.data != gen.o,
self.error_count.eq(self.error_count + 1) NextValue(self.err_count, self.err_count + 1)
),
If(data_counter == (self.length-1),
NextState("IDLE")
)
) )
) )
self.comb += data_counter_ce.eq(dma.source.valid)
self.comb += self.done.eq(~data_enable & ~address_enable) self.comb += self.done.eq(cmd_fsm.ongoing("IDLE") &
data_fsm.ongoing("IDLE"))
class LiteDRAMBISTChecker(Module, AutoCSR): class LiteDRAMBISTChecker(Module, AutoCSR):
@ -195,7 +196,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
self.done = CSRStatus() self.done = CSRStatus()
self.base = CSRStorage(dram_port.aw) self.base = CSRStorage(dram_port.aw)
self.length = CSRStorage(dram_port.aw) self.length = CSRStorage(dram_port.aw)
self.error_count = CSRStatus(32) self.err_count = CSRStatus(32)
# # # # # #
@ -211,8 +212,8 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
base_sync = BusSynchronizer(dram_port.aw, "sys", cd) base_sync = BusSynchronizer(dram_port.aw, "sys", cd)
length_sync = BusSynchronizer(dram_port.aw, "sys", cd) length_sync = BusSynchronizer(dram_port.aw, "sys", cd)
error_count_sync = BusSynchronizer(32, cd, "sys") err_count_sync = BusSynchronizer(32, cd, "sys")
self.submodules += base_sync, length_sync, error_count_sync self.submodules += base_sync, length_sync, err_count_sync
self.comb += [ self.comb += [
reset_sync.i.eq(self.reset.re), reset_sync.i.eq(self.reset.re),
@ -230,6 +231,6 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
length_sync.i.eq(self.length.storage), length_sync.i.eq(self.length.storage),
core.length.eq(length_sync.o), core.length.eq(length_sync.o),
error_count_sync.i.eq(core.error_count), err_count_sync.i.eq(core.err_count),
self.error_count.status.eq(error_count_sync.o) self.err_count.status.eq(err_count_sync.o)
] ]