frontend/avalon: Decouple Cmd and Data-paths in BURST-READ (We don't need to wait rdata.valid to return to Idle).
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@ -53,8 +53,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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burst_count = Signal(9)
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address = Signal(port.address_width)
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address_offset = Signal(port.address_width)
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cmd_ready_seen = Signal()
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cmd_ready_count = Signal(9)
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self.comb += address_offset.eq(base_address >> log2_int(port.data_width//8))
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# Write Data-path.
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@ -85,7 +83,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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avalon.waitrequest.eq(1),
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NextValue(cmd_ready_seen, 0),
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# Start of Access.
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If(avalon.read | avalon.write,
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NextValue(burst_count, avalon.burstcount),
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@ -97,7 +94,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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),
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If(avalon.read,
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avalon.waitrequest.eq(0),
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NextValue(cmd_ready_count, avalon.burstcount),
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NextState("BURST-READ")
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)
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# Single Access.
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@ -153,19 +149,14 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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avalon.waitrequest.eq(1),
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port.cmd.addr.eq(address),
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port.cmd.we.eq(0),
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port.cmd.valid.eq(~cmd_ready_seen),
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If(port.cmd.ready,
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If(cmd_ready_count == 1,
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NextValue(cmd_ready_seen, 1)
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),
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NextValue(cmd_ready_count, cmd_ready_count - 1),
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NextValue(address, address + burst_increment)
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),
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If(port.rdata.valid,
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If(burst_count == 1,
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port.cmd.valid.eq(1),
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port.cmd.last.eq(burst_count == 1),
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If(port.cmd.valid & port.cmd.ready,
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If(port.cmd.last,
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NextState("IDLE")
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),
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NextValue(burst_count, burst_count - 1)
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).Else(
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NextValue(burst_count, burst_count - 1),
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NextValue(address, address + burst_increment)
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)
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)
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)
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