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phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).

This commit is contained in:
Florent Kermarrec 2021-01-27 18:36:53 +01:00
parent 562cd3207c
commit 5a114be7e5
1 changed files with 4 additions and 2 deletions
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6
litedram/phy/ecp5ddrphy.py
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@ -116,7 +116,8 @@ class ECP5DDRPHY(Module, AutoCSR):
sys_clk_freq = 100e6, sys_clk_freq = 100e6,
cl = None, cl = None,
cwl = None, cwl = None,
cmd_delay = 0): cmd_delay = 0,
clk_polarity = 0):
assert isinstance(cmd_delay, int) and cmd_delay < 128 assert isinstance(cmd_delay, int) and cmd_delay < 128
pads = PHYPadsCombiner(pads) pads = PHYPadsCombiner(pads)
memtype = "DDR3" memtype = "DDR3"
@ -181,13 +182,14 @@ class ECP5DDRPHY(Module, AutoCSR):
pads.sel_group(pads_group) pads.sel_group(pads_group)
# Clock -------------------------------------------------------------------------------- # Clock --------------------------------------------------------------------------------
clk_pattern = {0: 0b1010, 1: 0b0101}[clk_polarity]
for i in range(len(pads.clk_p)): for i in range(len(pads.clk_p)):
pad_oddrx2f = Signal() pad_oddrx2f = Signal()
self.specials += Instance("ODDRX2F", self.specials += Instance("ODDRX2F",
i_RST = ResetSignal("sys"), i_RST = ResetSignal("sys"),
i_SCLK = ClockSignal("sys"), i_SCLK = ClockSignal("sys"),
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
**{f"i_D{n}": (0b1010 >> n) & 0b1 for n in range(4)}, **{f"i_D{n}": (clk_pattern >> n) & 0b1 for n in range(4)},
o_Q = pad_oddrx2f o_Q = pad_oddrx2f
) )
self.specials += Instance("DELAYG", self.specials += Instance("DELAYG",