test: add frontend.fifo tests
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Jędrzej Boczar
parent
72b91a8fb7
commit
5d5bff3425
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@ -10,37 +10,238 @@ from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMNativeWritePort
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from litedram.common import LiteDRAMNativeReadPort
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from litedram.frontend.fifo import LiteDRAMFIFO
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from litedram.frontend.fifo import LiteDRAMFIFO, \
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_LiteDRAMFIFOCtrl, _LiteDRAMFIFOWriter, _LiteDRAMFIFOReader
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from test.common import *
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class FIFODUT(Module):
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class TestFIFO(unittest.TestCase):
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@passive
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def fifo_ctrl_flag_checker(self, fifo_ctrl, write_threshold, read_threshold):
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while True:
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level = (yield fifo_ctrl.level)
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self.assertEqual((yield fifo_ctrl.writable), level < write_threshold)
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self.assertEqual((yield fifo_ctrl.readable), level > read_threshold)
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yield
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# _LiteDRAMFIFOCtrl ----------------------------------------------------------------------------
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def test_fifo_ctrl(self):
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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def main_generator():
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self.assertEqual((yield dut.level), 0)
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self.assertEqual((yield dut.write_address), 0)
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self.assertEqual((yield dut.read_address), 0)
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# ignore readable/writable
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# write address
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yield dut.write.eq(1)
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yield
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# write_address gets updated 1 cycle later
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for i in range(24 - 1):
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self.assertEqual((yield dut.write_address), i % 16)
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yield
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yield dut.write.eq(0)
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yield
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self.assertEqual((yield dut.write_address), 24 % 16)
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# read address
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yield dut.read.eq(1)
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yield
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for i in range(24 - 1):
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self.assertEqual((yield dut.read_address), i % 16)
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yield
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yield dut.read.eq(0)
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yield
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self.assertEqual((yield dut.read_address), 24 % 16)
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# level
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def check_level_diff(write, read, diff):
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level = (yield dut.level)
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yield dut.write.eq(write)
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yield dut.read.eq(read)
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yield
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yield dut.write.eq(0)
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yield dut.read.eq(0)
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yield
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self.assertEqual((yield dut.level), level + diff)
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check_level_diff(write=1, read=0, diff=+1)
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check_level_diff(write=1, read=1, diff=+0)
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check_level_diff(write=0, read=1, diff=-1)
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generators = [
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main_generator(),
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self.fifo_ctrl_flag_checker(dut, write_threshold=16, read_threshold=0),
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]
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run_simulation(dut, generators)
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# _LiteDRAMFIFOWriter --------------------------------------------------------------------------
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def fifo_writer_test(self, depth, sequence_len, write_threshold):
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth, read_threshold=0,
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write_threshold=write_threshold)
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writer = _LiteDRAMFIFOWriter(data_width=32, port=self.port, ctrl=ctrl)
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self.submodules.ctrl = ctrl
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self.submodules.writer = writer
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self.memory = DRAMMemory(32, 128)
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assert 8 + sequence_len <= len(self.memory.mem)
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write_data = [seed_to_data(i) for i in range(sequence_len)]
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def generator(dut):
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for data in write_data:
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yield dut.writer.sink.valid.eq(1)
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yield dut.writer.sink.data.eq(data)
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yield
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while (yield dut.writer.sink.ready) == 0:
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yield
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yield dut.writer.sink.valid.eq(0)
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for _ in range(16):
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yield
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dut = DUT()
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generators = [
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generator(dut),
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dut.memory.write_handler(dut.port),
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self.fifo_ctrl_flag_checker(dut.ctrl,
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write_threshold=write_threshold, read_threshold=0),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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mem_expected = [0] * len(dut.memory.mem)
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for i, data in enumerate(write_data):
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mem_expected[8 + i%depth] = data
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self.assertEqual(dut.memory.mem, mem_expected)
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def test_fifo_writer_sequence(self):
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self.fifo_writer_test(sequence_len=48, depth=64, write_threshold=64)
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def test_fifo_writer_address_wraps(self):
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=64)
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def test_fifo_writer_stops_after_threshold(self):
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with self.assertRaises(TimeoutError):
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=32)
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# _LiteDRAMFIFOReader --------------------------------------------------------------------------
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def fifo_reader_test(self, depth, sequence_len, read_threshold, inital_writes=0):
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memory_data = [seed_to_data(i) for i in range(128)]
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read_data = []
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth, read_threshold=read_threshold,
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write_threshold=depth)
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reader = _LiteDRAMFIFOReader(data_width=32, port=self.port, ctrl=ctrl)
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self.submodules.ctrl = ctrl
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self.submodules.reader = reader
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self.memory = DRAMMemory(32, len(memory_data), init=memory_data)
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assert 8 + sequence_len <= len(self.memory.mem)
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def reader(dut):
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# fake writing to fifo
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yield dut.ctrl.write.eq(1)
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for _ in range(inital_writes):
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yield
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yield dut.ctrl.write.eq(0)
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yield
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for _ in range(sequence_len):
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# fake single write
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yield dut.ctrl.write.eq(1)
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yield
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yield dut.ctrl.write.eq(0)
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while (yield dut.reader.source.valid) == 0:
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yield
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read_data.append((yield dut.reader.source.data))
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yield dut.reader.source.ready.eq(1)
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yield
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yield dut.reader.source.ready.eq(0)
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yield
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dut = DUT()
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generators = [
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reader(dut),
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dut.memory.read_handler(dut.port),
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self.fifo_ctrl_flag_checker(dut.ctrl, write_threshold=depth,
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read_threshold=read_threshold),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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read_data_expected = [memory_data[8 + i%depth] for i in range(sequence_len)]
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self.assertEqual(read_data, read_data_expected)
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def test_fifo_reader_sequence(self):
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self.fifo_reader_test(sequence_len=48, depth=64, read_threshold=0)
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def test_fifo_reader_address_wraps(self):
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=0)
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def test_fifo_reader_requires_threshold(self):
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with self.assertRaises(TimeoutError):
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=8)
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# will work after we perform the initial writes
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=8, inital_writes=8)
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# LiteDRAMFIFO ---------------------------------------------------------------------------------
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def test_fifo_default_thresholds(self):
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# defaults: read_threshold=0, write_threshold=depth
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read_threshold, write_threshold = (0, 128)
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write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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fifo = LiteDRAMFIFO(data_width=32, base=0, depth=write_threshold,
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write_port=write_port, read_port=read_port)
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def generator():
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yield write_port.cmd.ready.eq(1)
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yield write_port.wdata.ready.eq(1)
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for i in range(write_threshold):
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yield fifo.sink.valid.eq(1)
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yield fifo.sink.data.eq(0)
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yield
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while (yield fifo.sink.ready) == 0:
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yield
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yield
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checker = self.fifo_ctrl_flag_checker(fifo.ctrl, write_threshold, read_threshold)
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run_simulation(fifo, [generator(), checker])
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def test_fifo(self):
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class DUT(Module):
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def __init__(self):
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# ports
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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# fifo
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self.submodules.fifo = LiteDRAMFIFO(
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data_width = 32,
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depth = 64,
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base = 0,
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depth = 32,
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base = 16,
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write_port = self.write_port,
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read_port = self.read_port,
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read_threshold = 8,
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write_threshold = 64-8
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write_threshold = 32 - 8
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)
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# memory
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self.memory = DRAMMemory(32, 256)
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self.memory = DRAMMemory(32, 128)
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class TestFIFO(unittest.TestCase):
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def test_fifo(self):
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def generator(dut, valid_random=90):
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prng = random.Random(42)
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for i in range(128 + 8):
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# we need 8 more writes to account for read_threshold=8
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for i in range(64 + 8):
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while prng.randrange(100) < valid_random:
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yield
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yield dut.fifo.sink.valid.eq(1)
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@ -52,7 +253,7 @@ class TestFIFO(unittest.TestCase):
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def checker(dut, ready_random=90):
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prng = random.Random(42)
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for i in range(128):
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for i in range(64):
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yield dut.fifo.source.ready.eq(0)
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yield
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while (yield dut.fifo.source.valid) != 1:
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@ -63,7 +264,7 @@ class TestFIFO(unittest.TestCase):
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self.assertEqual((yield dut.fifo.source.data), i)
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yield
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dut = FIFODUT()
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dut = DUT()
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generators = [
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generator(dut),
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checker(dut),
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