mirror of
https://github.com/enjoy-digital/litedram.git
synced 2025-01-04 09:52:25 -05:00
litedram_gen: improve flexibility to define user ports
This commit is contained in:
Florent Kermarrec
parent
76caff5417
commit
61b19e2aaf
4 changed files with 97 additions and 58 deletions
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@ -29,12 +29,23 @@
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports_nb": 2, # Number of user ports
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"user_ports_type": "axi", # Type of ports (axi, wishbone, native)
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"user_ports_id_width": 32, # AXI identifier width
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# User FIFOs ---------------------------------------------------------------
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"user_fifos_nb": 1, # Number of user fifos
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"user_ports": {
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"axi_0" : {
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"type": "axi",
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"id_width": 32,
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},
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"wishbone_0" : {
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"type": "wishbone",
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},
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"native_0" : {
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"type": "native",
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},
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"fifo_0" : {
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"type": "fifo",
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"base": 0x00000000,
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"depth": 0x01000000,
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},
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},
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# CSR Port -----------------------------------------------------------------
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"csr_expose": "False", # Expose CSR bus as I/Os
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@ -29,9 +29,23 @@
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports_nb": 2, # Number of user ports
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"user_ports_type": "axi", # Type of ports (axi, wishbone, native)
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"user_ports_id_width": 32, # AXI identifier width
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"user_ports": {
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"axi_0" : {
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"type": "axi",
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"id_width": 32,
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},
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"wishbone_0" : {
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"type": "wishbone",
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},
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"native_0" : {
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"type": "native",
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},
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"fifo_0" : {
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"type": "fifo",
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"base": 0x00000000,
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"depth": 0x01000000,
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},
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},
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# CSR Port -----------------------------------------------------------------
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"csr_expose": "False", # Expose CSR bus as I/Os
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@ -24,9 +24,23 @@
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports_nb": 2, # Number of user ports
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"user_ports_type": "axi", # Type of ports (axi, wishbone, native)
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"user_ports_id_width": 32, # AXI identifier width
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"user_ports": {
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"axi_0" : {
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"type": "axi",
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"id_width": 32,
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},
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"wishbone_0" : {
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"type": "wishbone",
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},
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"native_0" : {
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"type": "native",
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},
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"fifo_0" : {
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"type": "fifo",
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"base": 0x00000000,
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"depth": 0x01000000,
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},
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},
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# CSR Port -----------------------------------------------------------------
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"csr_expose": "False", # Expose CSR bus as I/Os
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@ -112,7 +112,7 @@ def get_csr_ios(aw, dw):
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def get_native_user_port_ios(_id, aw, dw):
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return [
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("user_port", _id,
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("user_port_{}".format(_id), 0,
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# cmd
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Subsignal("cmd_valid", Pins(1)),
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Subsignal("cmd_ready", Pins(1)),
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@ -134,7 +134,7 @@ def get_native_user_port_ios(_id, aw, dw):
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def get_wishbone_user_port_ios(_id, aw, dw):
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return [
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("user_port", _id,
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("user_port_{}".format(_id), 0,
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Subsignal("adr", Pins(aw)),
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Subsignal("dat_w", Pins(dw)),
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Subsignal("dat_r", Pins(dw)),
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@ -149,7 +149,7 @@ def get_wishbone_user_port_ios(_id, aw, dw):
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def get_axi_user_port_ios(_id, aw, dw, iw):
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return [
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("user_port", _id,
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("user_port_{}".format(_id), 0,
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# aw
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Subsignal("aw_valid", Pins(1)),
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Subsignal("aw_ready", Pins(1)),
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@ -191,9 +191,9 @@ def get_axi_user_port_ios(_id, aw, dw, iw):
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),
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]
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def get_user_fifo_ios(_id, dw):
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def get_fifo_user_port_ios(_id, dw):
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return [
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("user_fifo", _id,
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("user_fifo_{}".format(_id), 0,
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# in
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Subsignal("in_valid", Pins(1)),
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Subsignal("in_ready", Pins(1)),
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@ -348,13 +348,14 @@ class LiteDRAMCore(SoCSDRAM):
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platform.request("user_clk").eq(ClockSignal()),
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platform.request("user_rst").eq(ResetSignal())
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]
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if core_config["user_ports_type"] == "native":
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for i in range(core_config["user_ports_nb"]):
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for name, port in core_config["user_ports"].items():
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# Native -------------------------------------------------------------------------------
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if port["type"] == "native":
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user_port = self.sdram.crossbar.get_port()
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platform.add_extension(get_native_user_port_ios(i,
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platform.add_extension(get_native_user_port_ios(name,
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user_port.address_width,
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user_port.data_width))
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_user_port_io = platform.request("user_port", i)
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_user_port_io = platform.request("user_port_{}".format(name))
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self.comb += [
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# cmd
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user_port.cmd.valid.eq(_user_port_io.cmd_valid),
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@ -373,18 +374,18 @@ class LiteDRAMCore(SoCSDRAM):
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user_port.rdata.ready.eq(_user_port_io.rdata_ready),
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_user_port_io.rdata_data.eq(user_port.rdata.data),
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]
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elif core_config["user_ports_type"] == "wishbone":
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for i in range(core_config["user_ports_nb"]):
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# Wishbone -----------------------------------------------------------------------------
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elif port["type"] == "wishbone":
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user_port = self.sdram.crossbar.get_port()
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wb_port = wishbone.Interface(
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user_port.data_width,
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user_port.address_width)
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wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
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self.submodules += wishbone2native
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platform.add_extension(get_wishbone_user_port_ios(i,
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platform.add_extension(get_wishbone_user_port_ios(name,
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len(wb_port.adr),
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len(wb_port.dat_w)))
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_wb_port_io = platform.request("user_port", i)
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_wb_port_io = platform.request("user_port_{}".format(name))
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self.comb += [
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wb_port.adr.eq(_wb_port_io.adr),
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wb_port.dat_w.eq(_wb_port_io.dat_w),
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@ -396,20 +397,20 @@ class LiteDRAMCore(SoCSDRAM):
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wb_port.we.eq(_wb_port_io.we),
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_wb_port_io.err.eq(wb_port.err),
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]
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elif core_config["user_ports_type"] == "axi":
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for i in range(core_config["user_ports_nb"]):
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# AXI ----------------------------------------------------------------------------------
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elif port["type"] == "axi":
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user_port = self.sdram.crossbar.get_port()
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axi_port = LiteDRAMAXIPort(
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user_port.data_width,
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user_port.address_width + log2_int(user_port.data_width//8),
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core_config["user_ports_id_width"])
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port["id_width"])
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axi2native = LiteDRAMAXI2Native(axi_port, user_port)
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self.submodules += axi2native
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platform.add_extension(get_axi_user_port_ios(i,
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platform.add_extension(get_axi_user_port_ios(name,
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axi_port.address_width,
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axi_port.data_width,
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core_config["user_ports_id_width"]))
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_axi_port_io = platform.request("user_port", i)
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port["id_width"]))
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_axi_port_io = platform.request("user_port_{}".format(name))
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self.comb += [
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# aw
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axi_port.aw.valid.eq(_axi_port_io.aw_valid),
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@ -450,34 +451,33 @@ class LiteDRAMCore(SoCSDRAM):
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_axi_port_io.r_data.eq(axi_port.r.data),
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_axi_port_io.r_id.eq(axi_port.r.id),
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]
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else:
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raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))
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# FIFO ---------------------------------------------------------------------------------
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elif port["type"] == "fifo":
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platform.add_extension(get_fifo_user_port_ios(name, user_port.data_width))
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_user_fifo_io = platform.request("user_fifo_{}".format(name))
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fifo = LiteDRAMFIFO(
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data_width = user_port.data_width,
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base = port["base"],
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depth = port["depth"],
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write_port = self.sdram.crossbar.get_port("write"),
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write_threshold = port["depth"] - 32, # FIXME
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read_port = self.sdram.crossbar.get_port("read"),
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read_threshold = 32 # FIXME
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)
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self.submodules += fifo
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self.comb += [
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# in
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fifo.sink.valid.eq(_user_fifo_io.in_valid),
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_user_fifo_io.in_ready.eq(fifo.sink.ready),
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fifo.sink.data.eq(_user_fifo_io.in_data),
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# User FIFOs -------------------------------------------------------------------------------
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for i in range(core_config.get("user_fifos_nb", 0)):
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platform.add_extension(get_user_fifo_ios(i, user_port.data_width))
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_user_fifo_io = platform.request("user_fifo", i)
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fifo = LiteDRAMFIFO(
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data_width = user_port.data_width,
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base = 0x00000000, # FIXME
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depth = 0x01000000, # FIXME
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write_port = self.sdram.crossbar.get_port("write"),
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write_threshold = 0x01000000 - 32, # FIXME
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read_port = self.sdram.crossbar.get_port("read"),
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read_threshold = 32 # FIXME
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)
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self.submodules += fifo
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self.comb += [
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# in
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fifo.sink.valid.eq(_user_fifo_io.in_valid),
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_user_fifo_io.in_ready.eq(fifo.sink.ready),
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fifo.sink.data.eq(_user_fifo_io.in_data),
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# out
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_user_fifo_io.out_valid.eq(fifo.source.valid),
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fifo.source.ready.eq(_user_fifo_io.out_ready),
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_user_fifo_io.out_data.eq(fifo.source.data),
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]
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# out
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_user_fifo_io.out_valid.eq(fifo.source.valid),
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fifo.source.ready.eq(_user_fifo_io.out_ready),
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_user_fifo_io.out_data.eq(fifo.source.data),
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]
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else:
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raise ValueError("Unsupported port type: {}".format(port["type"]))
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# Build --------------------------------------------------------------------------------------------
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