phy/kusddrphy: add dqs preamble/postamble instead of always toggling on oe_dqs
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da4651ff19
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@ -117,6 +117,8 @@ class KUSDDRPHY(Module, AutoCSR):
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# DQS and DM
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# DQS and DM
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oe_dqs = Signal()
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oe_dqs = Signal()
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oe_dqs_preamble = Signal()
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oe_dqs_postamble = Signal()
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dqs_serdes_pattern = Signal(8)
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dqs_serdes_pattern = Signal(8)
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self.comb += \
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self.comb += \
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If(self._wlevel_en.storage,
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If(self._wlevel_en.storage,
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@ -126,7 +128,13 @@ class KUSDDRPHY(Module, AutoCSR):
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dqs_serdes_pattern.eq(0b00000000)
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dqs_serdes_pattern.eq(0b00000000)
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)
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)
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).Else(
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).Else(
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dqs_serdes_pattern.eq(0b01010101)
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If(oe_dqs_preamble,
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dqs_serdes_pattern.eq(0b01000000)
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).Elif(oe_dqs_postamble,
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dqs_serdes_pattern.eq(0b00000001)
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).Else(
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dqs_serdes_pattern.eq(0b01010101)
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)
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)
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)
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for i in range(databits//8):
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for i in range(databits//8):
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dm_o_nodelay = Signal()
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dm_o_nodelay = Signal()
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@ -313,9 +321,12 @@ class KUSDDRPHY(Module, AutoCSR):
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wrphase = self.dfi.phases[self.settings.wrphase]
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wrphase = self.dfi.phases[self.settings.wrphase]
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3]))
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3]))
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self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3])
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self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3])
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self.sync += \
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self.sync += [
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oe_dqs_preamble.eq(last_wrdata_en[1]),
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oe_dqs_postamble.eq(last_wrdata_en[3]),
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If(self._wlevel_en.storage,
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If(self._wlevel_en.storage,
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oe_dqs.eq(1), oe_dq.eq(0)
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oe_dqs.eq(1), oe_dq.eq(0)
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).Else(
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).Else(
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oe_dqs.eq(oe), oe_dq.eq(oe)
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oe_dqs.eq(oe), oe_dq.eq(oe)
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)
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)
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]
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