phy/s6ddrphy: fix

2016-05-04 01:10:44 +02:00 · 2016-05-04 01:10:44 +02:00 · 68e4b9322c
parent bb67fdba57
commit 68e4b9322c
1 changed files with 2 additions and 2 deletions
--- a/litedram/phy/s6ddrphy.py
+++ b/litedram/phy/s6ddrphy.py
@ -51,7 +51,7 @@ class S6HalfRateDDRPHY(Module):
                write_latency=2
            )
        else:
-            self.settings = sdram_settings.PhySettings(
+            self.settings = PhySettings(
                memtype=memtype,
                dfi_databits=2*databits,
                nphases=nphases,
@ -407,7 +407,7 @@ class S6QuarterRateDDRPHY(Module):
        databits = len(pads.dq)
        nphases = 4

-        self.settings = sdram_settings.PhySettings(
+        self.settings = PhySettings(
            memtype="DDR3",
            dfi_databits=2*databits,
            nphases=nphases,