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lpddr4/init: initialize all More Registers (even if setting defaults)

This commit is contained in:
Jędrzej Boczar 2021-03-17 16:41:11 +01:00
parent 0ecb1340f5
commit 693695f067
1 changed files with 58 additions and 12 deletions
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70
litedram/init.py
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@ -477,6 +477,47 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
nwr = get_nwr()
odt_map = {
"disable": 0b000,
"RZQ/1": 0b001,
"RZQ/2": 0b010,
"RZQ/3": 0b011,
"RZQ/4": 0b100,
"RZQ/5": 0b101,
"RZQ/6": 0b110,
}
# Table 215: VREF Setting for Range[0] and Range[1] (LPDDR4 1.10V VDDQ)
# vref_ranges[range][percent_vddx]
vref_ranges = {
0: {
10.0: 0b000000, 10.4: 0b000001, 10.8: 0b000010, 11.2: 0b000011, 11.6: 0b000100,
12.0: 0b000101, 12.4: 0b000110, 12.8: 0b000111, 13.2: 0b001000, 13.6: 0b001001,
14.0: 0b001010, 14.4: 0b001011, 14.8: 0b001100, 15.2: 0b001101, 15.6: 0b001110,
16.0: 0b001111, 16.4: 0b010000, 16.8: 0b010001, 17.2: 0b010010, 17.6: 0b010011,
18.0: 0b010100, 18.4: 0b010101, 18.8: 0b010110, 19.2: 0b010111, 19.6: 0b011000,
20.0: 0b011001, 20.4: 0b011010, 20.8: 0b011011, 21.2: 0b011100, 21.6: 0b011101,
22.0: 0b011110, 22.4: 0b011111, 22.8: 0b100000, 23.2: 0b100001, 23.6: 0b100010,
24.0: 0b100011, 24.4: 0b100100, 24.8: 0b100101, 25.2: 0b100110, 25.6: 0b100111,
26.0: 0b101000, 26.4: 0b101001, 26.8: 0b101010, 27.2: 0b101011, 27.6: 0b101100,
28.0: 0b101101, 28.4: 0b101110, 28.8: 0b101111, 29.2: 0b110000, 29.6: 0b110001,
30.0: 0b110010,
},
1: {
22.0: 0b000000, 22.4: 0b000001, 22.8: 0b000010, 23.2: 0b000011, 23.6: 0b000100,
24.0: 0b000101, 24.4: 0b000110, 24.8: 0b000111, 25.2: 0b001000, 25.6: 0b001001,
26.0: 0b001010, 26.4: 0b001011, 26.8: 0b001100, 27.2: 0b001101, 27.6: 0b001110,
28.0: 0b001111, 28.4: 0b010000, 28.8: 0b010001, 29.2: 0b010010, 29.6: 0b010011,
30.0: 0b010100, 30.4: 0b010101, 30.8: 0b010110, 31.2: 0b010111, 31.6: 0b011000,
32.0: 0b011001, 32.4: 0b011010, 32.8: 0b011011, 33.2: 0b011100, 33.6: 0b011101,
34.0: 0b011110, 34.4: 0b011111, 34.8: 0b100000, 35.2: 0b100001, 35.6: 0b100010,
36.0: 0b100011, 36.4: 0b100100, 36.8: 0b100101, 37.2: 0b100110, 37.6: 0b100111,
38.0: 0b101000, 38.4: 0b101001, 38.8: 0b101010, 39.2: 0b101011, 39.6: 0b101100,
40.0: 0b101101, 40.4: 0b101110, 40.8: 0b101111, 41.2: 0b110000, 41.6: 0b110001,
42.0: 0b110010,
},
}
def reg(fields):
regval = 0
written = 0
@ -529,22 +570,27 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
(6, 1, 0), # use set A
(7, 1, 0), # write leveling disabled
])
# MR3 - defaults (DBI disabled)
odt_map = {
"disable": 0b000,
"RZQ/1": 0b001,
"RZQ/2": 0b010,
"RZQ/3": 0b011,
"RZQ/4": 0b100,
"RZQ/5": 0b101,
"RZQ/6": 0b110,
}
mr[3] = reg([ # defaults
(0, 1, 1),
(1, 1, 0),
(2, 1, 0),
(3, 3, odt_map["RZQ/6"]),
(6, 1, 0),
(7, 1, 0),
])
mr[11] = reg([
(0, 3, odt_map[dq_odt]),
(4, 3, odt_map[ca_odt]),
])
# MR12, MR14 - default Vref 50.3% Vddq
# MR13 - defaults (data mask enabled)
mr[12] = reg([
(0, 6, vref_ranges[1][27.2]), # Vref(CA) 27.2% VDD2
(6, 1, 1), # range[1]
])
mr[14] = reg([
(0, 6, vref_ranges[1][27.2]), # Vref(DQ) 27.2% VDDQ
(6, 1, 1), # range[1]
])
mr[13] = 0 # defaults (data mask enabled, frequency set point 0)
from litedram.phy.lpddr4.commands import SpecialCmd, MPC