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bench/genesys2: add uart_name parameter. 

Useful when Etherbone is just used to reload BIOS.
This commit is contained in:
Florent Kermarrec 2020-09-14 18:43:33 +02:00
parent f5184b41b5
commit 6a5f2fdb09
1 changed files with 6 additions and 4 deletions
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10
bench/genesys2.py
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@ -59,7 +59,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ---------------------------------------------------------------------------------------- # Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore): class BenchSoC(SoCCore):
def __init__(self, sys_clk_freq=int(175e6)): def __init__(self, uart_name="serial", sys_clk_freq=int(175e6)):
platform = genesys2.Platform() platform = genesys2.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -67,7 +67,7 @@ class BenchSoC(SoCCore):
integrated_rom_size = 0x8000, integrated_rom_size = 0x8000,
integrated_rom_mode = "rw", integrated_rom_mode = "rw",
csr_data_width = 32, csr_data_width = 32,
uart_name = "crossover") uart_name = uart_name)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -77,7 +77,8 @@ class BenchSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
cmd_latency = 0)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
@ -86,7 +87,8 @@ class BenchSoC(SoCCore):
) )
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") if uart_name != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(