phy/usddrphy: simplify commands.
This commit is contained in:
Florent Kermarrec
parent
1d756cb209
commit
6b0591920b
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@ -165,121 +165,59 @@ class USDDRPHY(Module, AutoCSR):
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)
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]
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# Addresses and Commands ---------------------------------------------------------------
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for i in range(addressbits if memtype=="DDR3" else addressbits-3):
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a_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal() | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = Cat(*[dfi.phases[n//2].address[i] for n in range(8)]),
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o_OQ = a_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = a_o_nodelay,
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o_DATAOUT = pads.a[i],
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)
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]
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# Commands -----------------------------------------------------------------------------
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pads_ba = Signal(bankbits)
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if memtype == "DDR3":
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self.comb += pads.ba.eq(pads_ba)
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else:
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self.comb += pads.ba.eq(pads_ba[:len(pads.ba)])
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self.comb += pads.bg.eq(pads_ba[len(pads.ba):])
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for i in range(bankbits):
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ba_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal() | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = Cat(*[dfi.phases[n//2].bank[i] for n in range(8)]),
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o_OQ = ba_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = ba_o_nodelay,
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o_DATAOUT = pads_ba[i],
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)
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]
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commands = {
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"a" : "address",
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pads_ba : "bank",
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"ras_n" : "ras_n" ,
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"cas_n" : "cas_n" ,
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"we_n" : "we_n" ,
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"cke" : "cke" ,
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"odt" : "odt" ,
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}
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if hasattr(pads, "reset_n"): commands.update({"reset_n" : "reset_n"})
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if hasattr(pads, "cs_n") : commands.update({"cs_n" : "cs_n"})
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if hasattr(pads, "act_n") : commands.update({"act_n" : "act_n"})
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for pad_name, dfi_name in commands.items():
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pad = pad_name if isinstance(pad_name, Signal) else getattr(pads, pad_name)
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for i in range(len(pad)):
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o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal() | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = Cat(*[getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)]),
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o_OQ = o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = o_nodelay,
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o_DATAOUT = pad[i],
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)
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]
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controls = ["ras_n", "cas_n", "we_n", "cke", "odt"]
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if hasattr(pads, "reset_n"):
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controls.append("reset_n")
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if hasattr(pads, "cs_n"):
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controls.append("cs_n")
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if hasattr(pads, "act_n"):
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controls.append("act_n")
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for name in controls:
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x_o_nodelay = Signal()
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self.specials += [
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Instance("OSERDESE3",
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p_SIM_DEVICE = device,
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal() | self._rst.storage,
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = Cat(*[getattr(dfi.phases[n//2], name) for n in range(8)]),
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o_OQ = x_o_nodelay,
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),
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Instance("ODELAYE3",
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p_SIM_DEVICE = device,
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p_CASCADE = "NONE",
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p_UPDATE_MODE = "ASYNC",
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_RST = self._cdly_rst.re | self._rst.storage,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = x_o_nodelay,
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o_DATAOUT = getattr(pads, name),
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)
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]
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self.comb += pads.ba.eq(pads_ba)
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if hasattr(pads, "bg"):
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self.comb += pads.bg.eq(pads_ba[len(pads.ba):])
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if hasattr(pads, "ten"):
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self.comb += pads.ten.eq(0)
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