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phy/usddrphy: simplify commands.

This commit is contained in:
Florent Kermarrec 2020-09-30 11:15:08 +02:00
parent 1d756cb209
commit 6b0591920b
1 changed files with 51 additions and 113 deletions
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164
litedram/phy/usddrphy.py
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@ -165,121 +165,59 @@ class USDDRPHY(Module, AutoCSR):
) )
] ]
# Addresses and Commands --------------------------------------------------------------- # Commands -----------------------------------------------------------------------------
for i in range(addressbits if memtype=="DDR3" else addressbits-3):
a_o_nodelay = Signal()
self.specials += [
Instance("OSERDESE3",
p_SIM_DEVICE = device,
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(*[dfi.phases[n//2].address[i] for n in range(8)]),
o_OQ = a_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
i_ODATAIN = a_o_nodelay,
o_DATAOUT = pads.a[i],
)
]
pads_ba = Signal(bankbits) pads_ba = Signal(bankbits)
if memtype == "DDR3": commands = {
self.comb += pads.ba.eq(pads_ba) "a" : "address",
else: pads_ba : "bank",
self.comb += pads.ba.eq(pads_ba[:len(pads.ba)]) "ras_n" : "ras_n" ,
self.comb += pads.bg.eq(pads_ba[len(pads.ba):]) "cas_n" : "cas_n" ,
for i in range(bankbits): "we_n" : "we_n" ,
ba_o_nodelay = Signal() "cke" : "cke" ,
self.specials += [ "odt" : "odt" ,
Instance("OSERDESE3", }
p_SIM_DEVICE = device, if hasattr(pads, "reset_n"): commands.update({"reset_n" : "reset_n"})
p_DATA_WIDTH = 8, if hasattr(pads, "cs_n") : commands.update({"cs_n" : "cs_n"})
p_INIT = 0, if hasattr(pads, "act_n") : commands.update({"act_n" : "act_n"})
p_IS_RST_INVERTED = 0, for pad_name, dfi_name in commands.items():
p_IS_CLK_INVERTED = 0, pad = pad_name if isinstance(pad_name, Signal) else getattr(pads, pad_name)
p_IS_CLKDIV_INVERTED = 0, for i in range(len(pad)):
i_RST = ResetSignal() | self._rst.storage, o_nodelay = Signal()
i_CLK = ClockSignal("sys4x"), self.specials += [
i_CLKDIV = ClockSignal(), Instance("OSERDESE3",
i_D = Cat(*[dfi.phases[n//2].bank[i] for n in range(8)]), p_SIM_DEVICE = device,
o_OQ = ba_o_nodelay, p_DATA_WIDTH = 8,
), p_INIT = 0,
Instance("ODELAYE3", p_IS_RST_INVERTED = 0,
p_SIM_DEVICE = device, p_IS_CLK_INVERTED = 0,
p_CASCADE = "NONE", p_IS_CLKDIV_INVERTED = 0,
p_UPDATE_MODE = "ASYNC", i_RST = ResetSignal() | self._rst.storage,
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6, i_CLK = ClockSignal("sys4x"),
p_DELAY_FORMAT = "TIME", i_CLKDIV = ClockSignal(),
p_DELAY_TYPE = "VARIABLE", i_D = Cat(*[getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)]),
p_DELAY_VALUE = 0, o_OQ = o_nodelay,
i_RST = self._cdly_rst.re | self._rst.storage, ),
i_CLK = ClockSignal(), Instance("ODELAYE3",
i_EN_VTC = self._en_vtc.storage, p_SIM_DEVICE = device,
i_CE = self._cdly_inc.re, p_CASCADE = "NONE",
i_INC = 1, p_UPDATE_MODE = "ASYNC",
i_ODATAIN = ba_o_nodelay, p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
o_DATAOUT = pads_ba[i], p_DELAY_FORMAT = "TIME",
) p_DELAY_TYPE = "VARIABLE",
] p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
i_ODATAIN = o_nodelay,
o_DATAOUT = pad[i],
)
]
controls = ["ras_n", "cas_n", "we_n", "cke", "odt"] self.comb += pads.ba.eq(pads_ba)
if hasattr(pads, "reset_n"): if hasattr(pads, "bg"):
controls.append("reset_n") self.comb += pads.bg.eq(pads_ba[len(pads.ba):])
if hasattr(pads, "cs_n"):
controls.append("cs_n")
if hasattr(pads, "act_n"):
controls.append("act_n")
for name in controls:
x_o_nodelay = Signal()
self.specials += [
Instance("OSERDESE3",
p_SIM_DEVICE = device,
p_DATA_WIDTH = 8,
p_INIT = 0,
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(*[getattr(dfi.phases[n//2], name) for n in range(8)]),
o_OQ = x_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
i_ODATAIN = x_o_nodelay,
o_DATAOUT = getattr(pads, name),
)
]
if hasattr(pads, "ten"): if hasattr(pads, "ten"):
self.comb += pads.ten.eq(0) self.comb += pads.ten.eq(0)