ddr4: Enable Data Mask for DDR4 memory and invert its polarity.
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1117068595
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6b9f1bd0d8
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@ -355,6 +355,8 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
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rtt_wr = "120ohm"
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rtt_wr = "120ohm"
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ron = "34ohm"
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ron = "34ohm"
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tdqs = 0
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tdqs = 0
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dm = 1
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assert not (dm and tdqs)
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# override electrical settings if specified
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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if hasattr(phy_settings, "rtt_nom"):
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@ -372,7 +374,7 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = format_mr3(timing_settings.fine_refresh_mode)
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mr3 = format_mr3(timing_settings.fine_refresh_mode)
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mr4 = 0
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mr4 = 0
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mr5 = 0
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mr5 = (dm << 10)
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mr6 = format_mr6(4) # FIXME: tCCD
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mr6 = format_mr6(4) # FIXME: tCCD
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rdimm_init = []
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rdimm_init = []
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@ -311,9 +311,12 @@ class USDDRPHY(Module, AutoCSR):
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# DM ---------------------------------------------------------------------------------------
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# DM ---------------------------------------------------------------------------------------
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for i in range(databits//8):
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for i in range(databits//8):
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if hasattr(pads, "dm"):
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if hasattr(pads, "dm"):
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dm_i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)])
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if memtype == "DDR4": # Inverted polarity for DDR4
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dm_i = ~dm_i
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dm_o_nodelay = Signal()
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dm_o_nodelay = Signal()
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dm_o_bitslip = BitSlip(8,
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dm_o_bitslip = BitSlip(8,
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i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
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i = dm_i,
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rst = (self._dly_sel.storage[i] & self._wdly_dq_bitslip_rst.re) | self._rst.storage,
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rst = (self._dly_sel.storage[i] & self._wdly_dq_bitslip_rst.re) | self._rst.storage,
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slp = self._dly_sel.storage[i] & self._wdly_dq_bitslip.re,
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slp = self._dly_sel.storage[i] & self._wdly_dq_bitslip.re,
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cycles = 1)
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cycles = 1)
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