ddr4: Enable Data Mask for DDR4 memory and invert its polarity.

litedram/init.py

@@ -355,6 +355,8 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
     rtt_wr  = "120ohm"
     ron     = "34ohm"
     tdqs    = 0
+    dm      = 1
+    assert not (dm and tdqs)
 
     # override electrical settings if specified
     if hasattr(phy_settings, "rtt_nom"):
@@ -372,7 +374,7 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
     mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
     mr3 = format_mr3(timing_settings.fine_refresh_mode)
     mr4 = 0
-    mr5 = 0
+    mr5 = (dm << 10)
     mr6 = format_mr6(4) # FIXME: tCCD
 
     rdimm_init = []

litedram/phy/usddrphy.py

@@ -311,9 +311,12 @@ class USDDRPHY(Module, AutoCSR):
         # DM ---------------------------------------------------------------------------------------
         for i in range(databits//8):
             if hasattr(pads, "dm"):
+                dm_i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)])
+                if memtype == "DDR4":  # Inverted polarity for DDR4
+                    dm_i = ~dm_i
                 dm_o_nodelay = Signal()
                 dm_o_bitslip = BitSlip(8,
-                    i      = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
+                    i      = dm_i,
                     rst    = (self._dly_sel.storage[i] & self._wdly_dq_bitslip_rst.re) | self._rst.storage,
                     slp    = self._dly_sel.storage[i] & self._wdly_dq_bitslip.re,
                     cycles = 1)