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core/refresher: reduce refresh period by one cycle
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parent
afb6d0a15e
commit
6c53996a70
2 changed files with 5 additions and 5 deletions
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@ -53,7 +53,7 @@ class RefreshTimer(Module):
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def __init__(self, trefi):
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def __init__(self, trefi):
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self.wait = wait = Signal()
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self.wait = wait = Signal()
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self.done = done = Signal()
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self.done = done = Signal()
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self.count = count = Signal(bits_for(trefi), reset=trefi)
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self.count = count = Signal(bits_for(trefi), reset=trefi-1)
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self.load = load = Signal()
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self.load = load = Signal()
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self.load_count = load_count = Signal(bits_for(trefi))
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self.load_count = load_count = Signal(bits_for(trefi))
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@ -44,14 +44,14 @@ class TestRefresh(unittest.TestCase):
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def refresh_timer_test(self, trefi):
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def refresh_timer_test(self, trefi):
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def generator(dut):
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def generator(dut):
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dut.errors = 0
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dut.errors = 0
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for i in range(16*(trefi + 1)):
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for i in range(16*trefi):
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yield
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if i%trefi == (trefi - 1):
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if i%(trefi + 1) == (trefi - 1):
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if (yield dut.refresh.done) != 1:
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if (yield dut.refresh.done) != 1:
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dut.errors += 1
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dut.errors += 1
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else:
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else:
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if (yield dut.refresh.done) != 0:
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if (yield dut.refresh.done) != 0:
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dut.errors += 1
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dut.errors += 1
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yield
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class DUT(Module):
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class DUT(Module):
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def __init__(self, trefi):
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def __init__(self, trefi):
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@ -93,7 +93,7 @@ class TestRefresh(unittest.TestCase):
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while (yield dut.cmd.valid) == 0:
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while (yield dut.cmd.valid) == 0:
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cmd_valid_gap += 1
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cmd_valid_gap += 1
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yield
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yield
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if cmd_valid_gap != (settings.timing.tREFI + 1):
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if cmd_valid_gap != settings.timing.tREFI:
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dut.errors += 1
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dut.errors += 1
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dut = Refresher(settings)
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dut = Refresher(settings)
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